[llvm] [MC][TableGen] Expand Opcode field of MCInstrDesc (PR #179652)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 4 05:01:44 PST 2026
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-webassembly
@llvm/pr-subscribers-backend-powerpc
Author: None (sstipano)
<details>
<summary>Changes</summary>
Increase width of Opcode to `int` from `short` to allow more capacity.
---
Patch is 38.52 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/179652.diff
15 Files Affected:
- (modified) llvm/include/llvm/MC/MCInstrDesc.h (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.h (+4-4)
- (modified) llvm/lib/Target/AMDGPU/R600InstrInfo.h (+1-1)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+3-3)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.h (+82-82)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp (+12-12)
- (modified) llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h (+5-5)
- (modified) llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp (+1-1)
- (modified) llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp (+1-1)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrInfo.h (+2-2)
- (modified) llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h (+3-3)
- (modified) llvm/test/TableGen/get-named-operand-idx.td (+5-5)
- (modified) llvm/utils/TableGen/AsmMatcherEmitter.cpp (+1-1)
- (modified) llvm/utils/TableGen/CodeGenMapTable.cpp (+1-1)
- (modified) llvm/utils/TableGen/InstrInfoEmitter.cpp (+10-10)
``````````diff
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h
index 69dd3e2848832..4b3765b5c2be5 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -203,7 +203,7 @@ class MCInstrDesc {
// the <Target>Insts table because they rely on knowing their own address to
// find other information elsewhere in the same table.
- unsigned short Opcode; // The opcode number
+ unsigned int Opcode; // The opcode number
unsigned short NumOperands; // Num of args (may be more if variable_ops)
unsigned char NumDefs; // Num of args that are definitions
unsigned char Size; // Number of bytes in encoding.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 2ccde3e661de5..94ab778bfa415 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -890,11 +890,11 @@ enum SMEMatrixType {
#undef TSFLAG_INSTR_FLAGS
#undef TSFLAG_SME_MATRIX_TYPE
-int getSVEPseudoMap(uint16_t Opcode);
-int getSVERevInstr(uint16_t Opcode);
-int getSVENonRevInstr(uint16_t Opcode);
+int getSVEPseudoMap(uint32_t Opcode);
+int getSVERevInstr(uint32_t Opcode);
+int getSVENonRevInstr(uint32_t Opcode);
-int getSMEPseudoMap(uint16_t Opcode);
+int getSMEPseudoMap(uint32_t Opcode);
}
} // end namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.h b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
index 68bbac103cb9a..b0a43b919915c 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
@@ -326,7 +326,7 @@ class R600InstrInfo final : public R600GenInstrInfo {
namespace R600 {
-int getLDSNoRetOp(uint16_t Opcode);
+int getLDSNoRetOp(uint32_t Opcode);
} //End namespace AMDGPU
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 9e3b683d10c45..4032a23f841bf 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4510,7 +4510,7 @@ bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
changesVGPRIndexingMode(MI);
}
-bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {
+bool SIInstrInfo::isAlwaysGDS(uint32_t Opcode) const {
return Opcode == AMDGPU::DS_ORDERED_COUNT ||
Opcode == AMDGPU::DS_ADD_GS_REG_RTN ||
Opcode == AMDGPU::DS_SUB_GS_REG_RTN || isGWS(Opcode);
@@ -5138,7 +5138,7 @@ bool SIInstrInfo::verifyCopy(const MachineInstr &MI,
bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
StringRef &ErrInfo) const {
- uint16_t Opcode = MI.getOpcode();
+ uint32_t Opcode = MI.getOpcode();
const MachineFunction *MF = MI.getMF();
const MachineRegisterInfo &MRI = MF->getRegInfo();
@@ -9945,7 +9945,7 @@ unsigned SIInstrInfo::getLiveRangeSplitOpcode(Register SrcReg,
}
bool SIInstrInfo::canAddToBBProlog(const MachineInstr &MI) const {
- uint16_t Opcode = MI.getOpcode();
+ uint32_t Opcode = MI.getOpcode();
// Check if it is SGPR spill or wwm-register spill Opcode.
if (isSGPRSpill(Opcode) || isWWMRegSpillOpcode(Opcode))
return true;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 05cf804d08ffc..30c63df8b52d8 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -461,7 +461,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SALU;
}
- bool isSALU(uint16_t Opcode) const {
+ bool isSALU(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SALU;
}
@@ -469,7 +469,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VALU;
}
- bool isVALU(uint16_t Opcode) const {
+ bool isVALU(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VALU;
}
@@ -477,7 +477,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return isMIMG(MI) || isVSAMPLE(MI) || isVIMAGE(MI);
}
- bool isImage(uint16_t Opcode) const {
+ bool isImage(uint32_t Opcode) const {
return isMIMG(Opcode) || isVSAMPLE(Opcode) || isVIMAGE(Opcode);
}
@@ -485,7 +485,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return isMUBUF(MI) || isMTBUF(MI) || isImage(MI) || isFLAT(MI);
}
- bool isVMEM(uint16_t Opcode) const {
+ bool isVMEM(uint32_t Opcode) const {
return isMUBUF(Opcode) || isMTBUF(Opcode) || isImage(Opcode);
}
@@ -493,7 +493,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
}
- bool isSOP1(uint16_t Opcode) const {
+ bool isSOP1(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOP1;
}
@@ -501,7 +501,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
}
- bool isSOP2(uint16_t Opcode) const {
+ bool isSOP2(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOP2;
}
@@ -509,7 +509,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
}
- bool isSOPC(uint16_t Opcode) const {
+ bool isSOPC(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOPC;
}
@@ -517,7 +517,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
}
- bool isSOPK(uint16_t Opcode) const {
+ bool isSOPK(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOPK;
}
@@ -525,7 +525,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
}
- bool isSOPP(uint16_t Opcode) const {
+ bool isSOPP(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOPP;
}
@@ -533,7 +533,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
}
- bool isPacked(uint16_t Opcode) const {
+ bool isPacked(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
}
@@ -541,7 +541,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
}
- bool isVOP1(uint16_t Opcode) const {
+ bool isVOP1(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VOP1;
}
@@ -549,7 +549,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
}
- bool isVOP2(uint16_t Opcode) const {
+ bool isVOP2(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VOP2;
}
@@ -559,13 +559,13 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
static bool isVOP3(const MachineInstr &MI) { return isVOP3(MI.getDesc()); }
- bool isVOP3(uint16_t Opcode) const { return isVOP3(get(Opcode)); }
+ bool isVOP3(uint32_t Opcode) const { return isVOP3(get(Opcode)); }
static bool isSDWA(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
}
- bool isSDWA(uint16_t Opcode) const {
+ bool isSDWA(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SDWA;
}
@@ -573,7 +573,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
}
- bool isVOPC(uint16_t Opcode) const {
+ bool isVOPC(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VOPC;
}
@@ -581,7 +581,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
}
- bool isMUBUF(uint16_t Opcode) const {
+ bool isMUBUF(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
}
@@ -589,7 +589,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
}
- bool isMTBUF(uint16_t Opcode) const {
+ bool isMTBUF(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
}
@@ -601,7 +601,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
}
- bool isSMRD(uint16_t Opcode) const {
+ bool isSMRD(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SMRD;
}
@@ -611,7 +611,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::DS;
}
- bool isDS(uint16_t Opcode) const {
+ bool isDS(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::DS;
}
@@ -620,7 +620,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
(MI.getDesc().TSFlags & SIInstrFlags::TENSOR_CNT);
}
- bool isLDSDMA(uint16_t Opcode) {
+ bool isLDSDMA(uint32_t Opcode) {
return (isVALU(Opcode) && (isMUBUF(Opcode) || isFLAT(Opcode))) ||
(get(Opcode).TSFlags & SIInstrFlags::TENSOR_CNT);
}
@@ -629,17 +629,17 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::GWS;
}
- bool isGWS(uint16_t Opcode) const {
+ bool isGWS(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::GWS;
}
- bool isAlwaysGDS(uint16_t Opcode) const;
+ bool isAlwaysGDS(uint32_t Opcode) const;
static bool isMIMG(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
}
- bool isMIMG(uint16_t Opcode) const {
+ bool isMIMG(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::MIMG;
}
@@ -647,7 +647,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VIMAGE;
}
- bool isVIMAGE(uint16_t Opcode) const {
+ bool isVIMAGE(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VIMAGE;
}
@@ -655,7 +655,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VSAMPLE;
}
- bool isVSAMPLE(uint16_t Opcode) const {
+ bool isVSAMPLE(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VSAMPLE;
}
@@ -663,7 +663,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
}
- bool isGather4(uint16_t Opcode) const {
+ bool isGather4(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::Gather4;
}
@@ -678,7 +678,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
}
- bool isSegmentSpecificFLAT(uint16_t Opcode) const {
+ bool isSegmentSpecificFLAT(uint32_t Opcode) const {
auto Flags = get(Opcode).TSFlags;
return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
}
@@ -687,7 +687,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
}
- bool isFLATGlobal(uint16_t Opcode) const {
+ bool isFLATGlobal(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
}
@@ -695,12 +695,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
}
- bool isFLATScratch(uint16_t Opcode) const {
+ bool isFLATScratch(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
}
// Any FLAT encoded instruction, including global_* and scratch_*.
- bool isFLAT(uint16_t Opcode) const {
+ bool isFLAT(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::FLAT;
}
@@ -716,7 +716,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
/// \returns true for FLAT instructions that can access LDS.
bool mayAccessLDSThroughFlat(const MachineInstr &MI) const;
- static bool isBlockLoadStore(uint16_t Opcode) {
+ static bool isBlockLoadStore(uint32_t Opcode) {
switch (Opcode) {
case AMDGPU::SI_BLOCK_SPILL_V1024_SAVE:
case AMDGPU::SI_BLOCK_SPILL_V1024_RESTORE:
@@ -788,7 +788,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
Target == AMDGPU::Exp::ET_DUAL_SRC_BLEND1;
}
- bool isEXP(uint16_t Opcode) const {
+ bool isEXP(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::EXP;
}
@@ -796,7 +796,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
}
- bool isAtomicNoRet(uint16_t Opcode) const {
+ bool isAtomicNoRet(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
}
@@ -804,7 +804,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
}
- bool isAtomicRet(uint16_t Opcode) const {
+ bool isAtomicRet(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
}
@@ -813,7 +813,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
SIInstrFlags::IsAtomicNoRet);
}
- bool isAtomic(uint16_t Opcode) const {
+ bool isAtomic(uint32_t Opcode) const {
return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
SIInstrFlags::IsAtomicNoRet);
}
@@ -842,7 +842,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::WQM;
}
- bool isWQM(uint16_t Opcode) const {
+ bool isWQM(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::WQM;
}
@@ -850,7 +850,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
}
- bool isDisableWQM(uint16_t Opcode) const {
+ bool isDisableWQM(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
}
@@ -865,7 +865,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
(isSpill(MI) && isVALU(MI));
}
- bool isVGPRSpill(uint16_t Opcode) const {
+ bool isVGPRSpill(uint32_t Opcode) const {
return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR &&
Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
(isSpill(Opcode) && isVALU(Opcode));
@@ -877,13 +877,13 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
(isSpill(MI) && isSALU(MI));
}
- bool isSGPRSpill(uint16_t Opcode) const {
+ bool isSGPRSpill(uint32_t Opcode) const {
return Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR ||
Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
(isSpill(Opcode) && isSALU(Opcode));
}
- bool isSpill(uint16_t Opcode) const {
+ bool isSpill(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::Spill;
}
@@ -893,7 +893,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
static bool isSpill(const MachineInstr &MI) { return isSpill(MI.getDesc()); }
- static bool isWWMRegSpillOpcode(uint16_t Opcode) {
+ static bool isWWMRegSpillOpcode(uint32_t Opcode) {
return Opcode == AMDGPU::SI_SPILL_WWM_V32_SAVE ||
Opcode == AMDGPU::SI_SPILL_WWM_AV32_SAVE ||
Opcode == AMDGPU::SI_SPILL_WWM_V32_RESTORE ||
@@ -909,7 +909,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::DPP;
}
- bool isDPP(uint16_t Opcode) const {
+ bool isDPP(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::DPP;
}
@@ -917,7 +917,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
}
- bool isTRANS(uint16_t Opcode) const {
+ bool isTRANS(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::TRANS;
}
@@ -925,7 +925,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
}
- bool isVOP3P(uint16_t Opcode) const {
+ bool isVOP3P(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
}
@@ -933,7 +933,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
}
- bool isVINTRP(uint16_t Opcode) const {
+ bool isVINTRP(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
}
@@ -943,14 +943,14 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
static bool isMAI(const MachineInstr &MI) { return isMAI(MI.getDesc()); }
- bool isMAI(uint16_t Opcode) const { return isMAI(get(Opcode)); }
+ bool isMAI(uint32_t Opcode) const { return isMAI(get(Opcode)); }
static bool isMFMA(const MachineInstr &MI) {
return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
}
- bool isMFMA(uint16_t Opcode) const {
+ bool isMFMA(uint32_t Opcode) const {
return isMAI(Opcode) && Opcode != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
Opcode != AMDGPU::V_ACCVGPR_READ_B32_e64;
}
@@ -963,7 +963,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::IsWMMA;
}
- bool isWMMA(uint16_t Opcode) const {
+ bool isWMMA(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsWMMA;
}
@@ -971,7 +971,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return isMFMA(MI) || isWMMA(MI) || isSWMMAC(MI);
}
- bool isMFMAorWMMA(uint16_t Opcode) const {
+ bool isMFMAorWMMA(uint32_t Opcode) const {
return isMFMA(Opcode) || isWMMA(Opcode) || isSWMMAC(Opcode);
}
@@ -979,11 +979,11 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::IsSWMMAC;
}
- bool isSWMMAC(uint16_t Opcode) const {
+ bool isSWMMAC(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsSWMMAC;
}
- bool isDOT(uint16_t Opcode) const {
+ bool isDOT(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
}
@@ -997,7 +997,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
}
- bool isLDSDIR(uint16_t Opcode) const {
+ bool isLDSDIR(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
}
@@ -1005,7 +1005,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
}
- bool isVINTERP(uint16_t Opcode) const {
+ bool isVINTERP(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
}
@@ -1025,7 +1025,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::ASYNC_CNT;
}
- bool usesASYNC_CNT(uint16_t Opcode) const {
+ bool usesASYNC_CNT(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::ASYNC_CNT;
}
@@ -1045,7 +1045,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
}
- bool isScalarStore(uint16_t Opcode) const {
+ bool isScalarStore(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
}
@@ -1053,7 +1053,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
}
- bool isFixedSize(uint16_t Opcode) const {
+ bool isFixedSize(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
}
@@ -1061,7 +1061,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
}
- bool hasFPClamp(uint16_t Opcode) const {
+ bool hasFPClamp(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
}
@@ -1081,7 +1081,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
}
- bool usesFPDPRounding(uint16_t Opcode) const {
+ bool usesFPDPRounding(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
}
@@ -1089,7 +1089,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
}
- bool isFPAtomic(uint16_t Opcode) const {
+ boo...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/179652
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