[llvm] [MC][TableGen] Expand Opcode field of MCInstrDesc (PR #179652)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Feb 4 05:01:13 PST 2026
https://github.com/sstipano created https://github.com/llvm/llvm-project/pull/179652
Increase width of Opcode to `int` from `short` to allow more capacity.
>From 8d560e87a4a09776736112d76037e1fce10a18f7 Mon Sep 17 00:00:00 2001
From: sstipano <sstipano7 at gmail.com>
Date: Wed, 4 Feb 2026 13:59:26 +0100
Subject: [PATCH] [MC][TableGen] Expand Opcode field of MCInstrDesc Increase
width of Opcode to `int` from `short` to allow more capacity.
---
llvm/include/llvm/MC/MCInstrDesc.h | 2 +-
llvm/lib/Target/AArch64/AArch64InstrInfo.h | 8 +-
llvm/lib/Target/AMDGPU/R600InstrInfo.h | 2 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 6 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.h | 164 +++++++++---------
.../Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 24 +--
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h | 10 +-
.../Target/PowerPC/PPCHazardRecognizers.cpp | 2 +-
llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp | 2 +-
llvm/lib/Target/SystemZ/SystemZInstrInfo.h | 4 +-
.../TargetInfo/WebAssemblyTargetInfo.h | 6 +-
llvm/test/TableGen/get-named-operand-idx.td | 10 +-
llvm/utils/TableGen/AsmMatcherEmitter.cpp | 2 +-
llvm/utils/TableGen/CodeGenMapTable.cpp | 2 +-
llvm/utils/TableGen/InstrInfoEmitter.cpp | 20 +--
15 files changed, 132 insertions(+), 132 deletions(-)
diff --git a/llvm/include/llvm/MC/MCInstrDesc.h b/llvm/include/llvm/MC/MCInstrDesc.h
index 69dd3e2848832..4b3765b5c2be5 100644
--- a/llvm/include/llvm/MC/MCInstrDesc.h
+++ b/llvm/include/llvm/MC/MCInstrDesc.h
@@ -203,7 +203,7 @@ class MCInstrDesc {
// the <Target>Insts table because they rely on knowing their own address to
// find other information elsewhere in the same table.
- unsigned short Opcode; // The opcode number
+ unsigned int Opcode; // The opcode number
unsigned short NumOperands; // Num of args (may be more if variable_ops)
unsigned char NumDefs; // Num of args that are definitions
unsigned char Size; // Number of bytes in encoding.
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
index 2ccde3e661de5..94ab778bfa415 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h
@@ -890,11 +890,11 @@ enum SMEMatrixType {
#undef TSFLAG_INSTR_FLAGS
#undef TSFLAG_SME_MATRIX_TYPE
-int getSVEPseudoMap(uint16_t Opcode);
-int getSVERevInstr(uint16_t Opcode);
-int getSVENonRevInstr(uint16_t Opcode);
+int getSVEPseudoMap(uint32_t Opcode);
+int getSVERevInstr(uint32_t Opcode);
+int getSVENonRevInstr(uint32_t Opcode);
-int getSMEPseudoMap(uint16_t Opcode);
+int getSMEPseudoMap(uint32_t Opcode);
}
} // end namespace llvm
diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.h b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
index 68bbac103cb9a..b0a43b919915c 100644
--- a/llvm/lib/Target/AMDGPU/R600InstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.h
@@ -326,7 +326,7 @@ class R600InstrInfo final : public R600GenInstrInfo {
namespace R600 {
-int getLDSNoRetOp(uint16_t Opcode);
+int getLDSNoRetOp(uint32_t Opcode);
} //End namespace AMDGPU
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 9e3b683d10c45..4032a23f841bf 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4510,7 +4510,7 @@ bool SIInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
changesVGPRIndexingMode(MI);
}
-bool SIInstrInfo::isAlwaysGDS(uint16_t Opcode) const {
+bool SIInstrInfo::isAlwaysGDS(uint32_t Opcode) const {
return Opcode == AMDGPU::DS_ORDERED_COUNT ||
Opcode == AMDGPU::DS_ADD_GS_REG_RTN ||
Opcode == AMDGPU::DS_SUB_GS_REG_RTN || isGWS(Opcode);
@@ -5138,7 +5138,7 @@ bool SIInstrInfo::verifyCopy(const MachineInstr &MI,
bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
StringRef &ErrInfo) const {
- uint16_t Opcode = MI.getOpcode();
+ uint32_t Opcode = MI.getOpcode();
const MachineFunction *MF = MI.getMF();
const MachineRegisterInfo &MRI = MF->getRegInfo();
@@ -9945,7 +9945,7 @@ unsigned SIInstrInfo::getLiveRangeSplitOpcode(Register SrcReg,
}
bool SIInstrInfo::canAddToBBProlog(const MachineInstr &MI) const {
- uint16_t Opcode = MI.getOpcode();
+ uint32_t Opcode = MI.getOpcode();
// Check if it is SGPR spill or wwm-register spill Opcode.
if (isSGPRSpill(Opcode) || isWWMRegSpillOpcode(Opcode))
return true;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 05cf804d08ffc..30c63df8b52d8 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -461,7 +461,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SALU;
}
- bool isSALU(uint16_t Opcode) const {
+ bool isSALU(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SALU;
}
@@ -469,7 +469,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VALU;
}
- bool isVALU(uint16_t Opcode) const {
+ bool isVALU(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VALU;
}
@@ -477,7 +477,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return isMIMG(MI) || isVSAMPLE(MI) || isVIMAGE(MI);
}
- bool isImage(uint16_t Opcode) const {
+ bool isImage(uint32_t Opcode) const {
return isMIMG(Opcode) || isVSAMPLE(Opcode) || isVIMAGE(Opcode);
}
@@ -485,7 +485,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return isMUBUF(MI) || isMTBUF(MI) || isImage(MI) || isFLAT(MI);
}
- bool isVMEM(uint16_t Opcode) const {
+ bool isVMEM(uint32_t Opcode) const {
return isMUBUF(Opcode) || isMTBUF(Opcode) || isImage(Opcode);
}
@@ -493,7 +493,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOP1;
}
- bool isSOP1(uint16_t Opcode) const {
+ bool isSOP1(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOP1;
}
@@ -501,7 +501,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOP2;
}
- bool isSOP2(uint16_t Opcode) const {
+ bool isSOP2(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOP2;
}
@@ -509,7 +509,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOPC;
}
- bool isSOPC(uint16_t Opcode) const {
+ bool isSOPC(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOPC;
}
@@ -517,7 +517,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOPK;
}
- bool isSOPK(uint16_t Opcode) const {
+ bool isSOPK(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOPK;
}
@@ -525,7 +525,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SOPP;
}
- bool isSOPP(uint16_t Opcode) const {
+ bool isSOPP(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SOPP;
}
@@ -533,7 +533,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::IsPacked;
}
- bool isPacked(uint16_t Opcode) const {
+ bool isPacked(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsPacked;
}
@@ -541,7 +541,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VOP1;
}
- bool isVOP1(uint16_t Opcode) const {
+ bool isVOP1(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VOP1;
}
@@ -549,7 +549,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VOP2;
}
- bool isVOP2(uint16_t Opcode) const {
+ bool isVOP2(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VOP2;
}
@@ -559,13 +559,13 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
static bool isVOP3(const MachineInstr &MI) { return isVOP3(MI.getDesc()); }
- bool isVOP3(uint16_t Opcode) const { return isVOP3(get(Opcode)); }
+ bool isVOP3(uint32_t Opcode) const { return isVOP3(get(Opcode)); }
static bool isSDWA(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::SDWA;
}
- bool isSDWA(uint16_t Opcode) const {
+ bool isSDWA(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SDWA;
}
@@ -573,7 +573,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VOPC;
}
- bool isVOPC(uint16_t Opcode) const {
+ bool isVOPC(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VOPC;
}
@@ -581,7 +581,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::MUBUF;
}
- bool isMUBUF(uint16_t Opcode) const {
+ bool isMUBUF(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::MUBUF;
}
@@ -589,7 +589,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::MTBUF;
}
- bool isMTBUF(uint16_t Opcode) const {
+ bool isMTBUF(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::MTBUF;
}
@@ -601,7 +601,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SMRD;
}
- bool isSMRD(uint16_t Opcode) const {
+ bool isSMRD(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SMRD;
}
@@ -611,7 +611,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::DS;
}
- bool isDS(uint16_t Opcode) const {
+ bool isDS(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::DS;
}
@@ -620,7 +620,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
(MI.getDesc().TSFlags & SIInstrFlags::TENSOR_CNT);
}
- bool isLDSDMA(uint16_t Opcode) {
+ bool isLDSDMA(uint32_t Opcode) {
return (isVALU(Opcode) && (isMUBUF(Opcode) || isFLAT(Opcode))) ||
(get(Opcode).TSFlags & SIInstrFlags::TENSOR_CNT);
}
@@ -629,17 +629,17 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::GWS;
}
- bool isGWS(uint16_t Opcode) const {
+ bool isGWS(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::GWS;
}
- bool isAlwaysGDS(uint16_t Opcode) const;
+ bool isAlwaysGDS(uint32_t Opcode) const;
static bool isMIMG(const MachineInstr &MI) {
return MI.getDesc().TSFlags & SIInstrFlags::MIMG;
}
- bool isMIMG(uint16_t Opcode) const {
+ bool isMIMG(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::MIMG;
}
@@ -647,7 +647,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VIMAGE;
}
- bool isVIMAGE(uint16_t Opcode) const {
+ bool isVIMAGE(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VIMAGE;
}
@@ -655,7 +655,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VSAMPLE;
}
- bool isVSAMPLE(uint16_t Opcode) const {
+ bool isVSAMPLE(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VSAMPLE;
}
@@ -663,7 +663,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::Gather4;
}
- bool isGather4(uint16_t Opcode) const {
+ bool isGather4(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::Gather4;
}
@@ -678,7 +678,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
}
- bool isSegmentSpecificFLAT(uint16_t Opcode) const {
+ bool isSegmentSpecificFLAT(uint32_t Opcode) const {
auto Flags = get(Opcode).TSFlags;
return Flags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
}
@@ -687,7 +687,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::FlatGlobal;
}
- bool isFLATGlobal(uint16_t Opcode) const {
+ bool isFLATGlobal(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::FlatGlobal;
}
@@ -695,12 +695,12 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::FlatScratch;
}
- bool isFLATScratch(uint16_t Opcode) const {
+ bool isFLATScratch(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::FlatScratch;
}
// Any FLAT encoded instruction, including global_* and scratch_*.
- bool isFLAT(uint16_t Opcode) const {
+ bool isFLAT(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::FLAT;
}
@@ -716,7 +716,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
/// \returns true for FLAT instructions that can access LDS.
bool mayAccessLDSThroughFlat(const MachineInstr &MI) const;
- static bool isBlockLoadStore(uint16_t Opcode) {
+ static bool isBlockLoadStore(uint32_t Opcode) {
switch (Opcode) {
case AMDGPU::SI_BLOCK_SPILL_V1024_SAVE:
case AMDGPU::SI_BLOCK_SPILL_V1024_RESTORE:
@@ -788,7 +788,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
Target == AMDGPU::Exp::ET_DUAL_SRC_BLEND1;
}
- bool isEXP(uint16_t Opcode) const {
+ bool isEXP(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::EXP;
}
@@ -796,7 +796,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicNoRet;
}
- bool isAtomicNoRet(uint16_t Opcode) const {
+ bool isAtomicNoRet(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsAtomicNoRet;
}
@@ -804,7 +804,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::IsAtomicRet;
}
- bool isAtomicRet(uint16_t Opcode) const {
+ bool isAtomicRet(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsAtomicRet;
}
@@ -813,7 +813,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
SIInstrFlags::IsAtomicNoRet);
}
- bool isAtomic(uint16_t Opcode) const {
+ bool isAtomic(uint32_t Opcode) const {
return get(Opcode).TSFlags & (SIInstrFlags::IsAtomicRet |
SIInstrFlags::IsAtomicNoRet);
}
@@ -842,7 +842,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::WQM;
}
- bool isWQM(uint16_t Opcode) const {
+ bool isWQM(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::WQM;
}
@@ -850,7 +850,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::DisableWQM;
}
- bool isDisableWQM(uint16_t Opcode) const {
+ bool isDisableWQM(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::DisableWQM;
}
@@ -865,7 +865,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
(isSpill(MI) && isVALU(MI));
}
- bool isVGPRSpill(uint16_t Opcode) const {
+ bool isVGPRSpill(uint32_t Opcode) const {
return Opcode != AMDGPU::SI_SPILL_S32_TO_VGPR &&
Opcode != AMDGPU::SI_RESTORE_S32_FROM_VGPR &&
(isSpill(Opcode) && isVALU(Opcode));
@@ -877,13 +877,13 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
(isSpill(MI) && isSALU(MI));
}
- bool isSGPRSpill(uint16_t Opcode) const {
+ bool isSGPRSpill(uint32_t Opcode) const {
return Opcode == AMDGPU::SI_SPILL_S32_TO_VGPR ||
Opcode == AMDGPU::SI_RESTORE_S32_FROM_VGPR ||
(isSpill(Opcode) && isSALU(Opcode));
}
- bool isSpill(uint16_t Opcode) const {
+ bool isSpill(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::Spill;
}
@@ -893,7 +893,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
static bool isSpill(const MachineInstr &MI) { return isSpill(MI.getDesc()); }
- static bool isWWMRegSpillOpcode(uint16_t Opcode) {
+ static bool isWWMRegSpillOpcode(uint32_t Opcode) {
return Opcode == AMDGPU::SI_SPILL_WWM_V32_SAVE ||
Opcode == AMDGPU::SI_SPILL_WWM_AV32_SAVE ||
Opcode == AMDGPU::SI_SPILL_WWM_V32_RESTORE ||
@@ -909,7 +909,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::DPP;
}
- bool isDPP(uint16_t Opcode) const {
+ bool isDPP(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::DPP;
}
@@ -917,7 +917,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::TRANS;
}
- bool isTRANS(uint16_t Opcode) const {
+ bool isTRANS(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::TRANS;
}
@@ -925,7 +925,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VOP3P;
}
- bool isVOP3P(uint16_t Opcode) const {
+ bool isVOP3P(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VOP3P;
}
@@ -933,7 +933,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VINTRP;
}
- bool isVINTRP(uint16_t Opcode) const {
+ bool isVINTRP(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VINTRP;
}
@@ -943,14 +943,14 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
static bool isMAI(const MachineInstr &MI) { return isMAI(MI.getDesc()); }
- bool isMAI(uint16_t Opcode) const { return isMAI(get(Opcode)); }
+ bool isMAI(uint32_t Opcode) const { return isMAI(get(Opcode)); }
static bool isMFMA(const MachineInstr &MI) {
return isMAI(MI) && MI.getOpcode() != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
MI.getOpcode() != AMDGPU::V_ACCVGPR_READ_B32_e64;
}
- bool isMFMA(uint16_t Opcode) const {
+ bool isMFMA(uint32_t Opcode) const {
return isMAI(Opcode) && Opcode != AMDGPU::V_ACCVGPR_WRITE_B32_e64 &&
Opcode != AMDGPU::V_ACCVGPR_READ_B32_e64;
}
@@ -963,7 +963,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::IsWMMA;
}
- bool isWMMA(uint16_t Opcode) const {
+ bool isWMMA(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsWMMA;
}
@@ -971,7 +971,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return isMFMA(MI) || isWMMA(MI) || isSWMMAC(MI);
}
- bool isMFMAorWMMA(uint16_t Opcode) const {
+ bool isMFMAorWMMA(uint32_t Opcode) const {
return isMFMA(Opcode) || isWMMA(Opcode) || isSWMMAC(Opcode);
}
@@ -979,11 +979,11 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::IsSWMMAC;
}
- bool isSWMMAC(uint16_t Opcode) const {
+ bool isSWMMAC(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsSWMMAC;
}
- bool isDOT(uint16_t Opcode) const {
+ bool isDOT(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::IsDOT;
}
@@ -997,7 +997,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::LDSDIR;
}
- bool isLDSDIR(uint16_t Opcode) const {
+ bool isLDSDIR(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::LDSDIR;
}
@@ -1005,7 +1005,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::VINTERP;
}
- bool isVINTERP(uint16_t Opcode) const {
+ bool isVINTERP(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::VINTERP;
}
@@ -1025,7 +1025,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::ASYNC_CNT;
}
- bool usesASYNC_CNT(uint16_t Opcode) const {
+ bool usesASYNC_CNT(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::ASYNC_CNT;
}
@@ -1045,7 +1045,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
}
- bool isScalarStore(uint16_t Opcode) const {
+ bool isScalarStore(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::SCALAR_STORE;
}
@@ -1053,7 +1053,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::FIXED_SIZE;
}
- bool isFixedSize(uint16_t Opcode) const {
+ bool isFixedSize(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::FIXED_SIZE;
}
@@ -1061,7 +1061,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::FPClamp;
}
- bool hasFPClamp(uint16_t Opcode) const {
+ bool hasFPClamp(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::FPClamp;
}
@@ -1081,7 +1081,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::FPDPRounding;
}
- bool usesFPDPRounding(uint16_t Opcode) const {
+ bool usesFPDPRounding(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::FPDPRounding;
}
@@ -1089,7 +1089,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::FPAtomic;
}
- bool isFPAtomic(uint16_t Opcode) const {
+ bool isFPAtomic(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::FPAtomic;
}
@@ -1134,7 +1134,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
return MI.getDesc().TSFlags & SIInstrFlags::TiedSourceNotRead;
}
- bool doesNotReadTiedSource(uint16_t Opcode) const {
+ bool doesNotReadTiedSource(uint32_t Opcode) const {
return get(Opcode).TSFlags & SIInstrFlags::TiedSourceNotRead;
}
@@ -1377,7 +1377,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
/// Return the size in bytes of the operand OpNo on the given
// instruction opcode.
- unsigned getOpSize(uint16_t Opcode, unsigned OpNo) const {
+ unsigned getOpSize(uint32_t Opcode, unsigned OpNo) const {
const MCOperandInfo &OpInfo = get(Opcode).operands()[OpNo];
if (OpInfo.RegClass == -1) {
@@ -1732,86 +1732,86 @@ bool execMayBeModifiedBeforeAnyUse(const MachineRegisterInfo &MRI,
namespace AMDGPU {
LLVM_READONLY
- int getVOPe64(uint16_t Opcode);
+ int getVOPe64(uint32_t Opcode);
LLVM_READONLY
- int getVOPe32(uint16_t Opcode);
+ int getVOPe32(uint32_t Opcode);
LLVM_READONLY
- int getSDWAOp(uint16_t Opcode);
+ int getSDWAOp(uint32_t Opcode);
LLVM_READONLY
- int getDPPOp32(uint16_t Opcode);
+ int getDPPOp32(uint32_t Opcode);
LLVM_READONLY
- int getDPPOp64(uint16_t Opcode);
+ int getDPPOp64(uint32_t Opcode);
LLVM_READONLY
- int getBasicFromSDWAOp(uint16_t Opcode);
+ int getBasicFromSDWAOp(uint32_t Opcode);
LLVM_READONLY
- int getCommuteRev(uint16_t Opcode);
+ int getCommuteRev(uint32_t Opcode);
LLVM_READONLY
- int getCommuteOrig(uint16_t Opcode);
+ int getCommuteOrig(uint32_t Opcode);
LLVM_READONLY
- int getAddr64Inst(uint16_t Opcode);
+ int getAddr64Inst(uint32_t Opcode);
/// Check if \p Opcode is an Addr64 opcode.
///
/// \returns \p Opcode if it is an Addr64 opcode, otherwise -1.
LLVM_READONLY
- int getIfAddr64Inst(uint16_t Opcode);
+ int getIfAddr64Inst(uint32_t Opcode);
LLVM_READONLY
- int getSOPKOp(uint16_t Opcode);
+ int getSOPKOp(uint32_t Opcode);
/// \returns SADDR form of a FLAT Global instruction given an \p Opcode
/// of a VADDR form.
LLVM_READONLY
- int getGlobalSaddrOp(uint16_t Opcode);
+ int getGlobalSaddrOp(uint32_t Opcode);
/// \returns VADDR form of a FLAT Global instruction given an \p Opcode
/// of a SADDR form.
LLVM_READONLY
- int getGlobalVaddrOp(uint16_t Opcode);
+ int getGlobalVaddrOp(uint32_t Opcode);
LLVM_READONLY
- int getVCMPXNoSDstOp(uint16_t Opcode);
+ int getVCMPXNoSDstOp(uint32_t Opcode);
/// \returns ST form with only immediate offset of a FLAT Scratch instruction
/// given an \p Opcode of an SS (SADDR) form.
LLVM_READONLY
- int getFlatScratchInstSTfromSS(uint16_t Opcode);
+ int getFlatScratchInstSTfromSS(uint32_t Opcode);
/// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
/// of an SVS (SADDR + VADDR) form.
LLVM_READONLY
- int getFlatScratchInstSVfromSVS(uint16_t Opcode);
+ int getFlatScratchInstSVfromSVS(uint32_t Opcode);
/// \returns SS (SADDR) form of a FLAT Scratch instruction given an \p Opcode
/// of an SV (VADDR) form.
LLVM_READONLY
- int getFlatScratchInstSSfromSV(uint16_t Opcode);
+ int getFlatScratchInstSSfromSV(uint32_t Opcode);
/// \returns SV (VADDR) form of a FLAT Scratch instruction given an \p Opcode
/// of an SS (SADDR) form.
LLVM_READONLY
- int getFlatScratchInstSVfromSS(uint16_t Opcode);
+ int getFlatScratchInstSVfromSS(uint32_t Opcode);
/// \returns earlyclobber version of a MAC MFMA is exists.
LLVM_READONLY
- int getMFMAEarlyClobberOp(uint16_t Opcode);
+ int getMFMAEarlyClobberOp(uint32_t Opcode);
/// \returns Version of an MFMA instruction which uses AGPRs for srcC and
/// vdst, given an \p Opcode of an MFMA which uses VGPRs for srcC/vdst.
LLVM_READONLY
- int getMFMASrcCVDstAGPROp(uint16_t Opcode);
+ int getMFMASrcCVDstAGPROp(uint32_t Opcode);
/// \returns v_cmpx version of a v_cmp instruction.
LLVM_READONLY
- int getVCMPXOpFromVCMP(uint16_t Opcode);
+ int getVCMPXOpFromVCMP(uint32_t Opcode);
const uint64_t RSRC_DATA_FORMAT = 0xf00000000000LL;
const uint64_t RSRC_ELEMENT_SIZE_SHIFT = (32 + 19);
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index c9f84708d8b32..76199591f40c1 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -355,7 +355,7 @@ unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
}
struct MUBUFInfo {
- uint16_t Opcode;
+ uint32_t Opcode;
uint16_t BaseOpcode;
uint8_t elements;
bool has_vaddr;
@@ -366,7 +366,7 @@ struct MUBUFInfo {
};
struct MTBUFInfo {
- uint16_t Opcode;
+ uint32_t Opcode;
uint16_t BaseOpcode;
uint8_t elements;
bool has_vaddr;
@@ -375,25 +375,25 @@ struct MTBUFInfo {
};
struct SMInfo {
- uint16_t Opcode;
+ uint32_t Opcode;
bool IsBuffer;
};
struct VOPInfo {
- uint16_t Opcode;
+ uint32_t Opcode;
bool IsSingle;
};
struct VOPC64DPPInfo {
- uint16_t Opcode;
+ uint32_t Opcode;
};
struct VOPCDPPAsmOnlyInfo {
- uint16_t Opcode;
+ uint32_t Opcode;
};
struct VOP3CDPPAsmOnlyInfo {
- uint16_t Opcode;
+ uint32_t Opcode;
};
struct VOPDComponentInfo {
@@ -404,7 +404,7 @@ struct VOPDComponentInfo {
};
struct VOPDInfo {
- uint16_t Opcode;
+ uint32_t Opcode;
uint16_t OpX;
uint16_t OpY;
uint16_t Subtarget;
@@ -412,7 +412,7 @@ struct VOPDInfo {
};
struct VOPTrue16Info {
- uint16_t Opcode;
+ uint32_t Opcode;
bool IsTrue16;
};
@@ -420,12 +420,12 @@ struct VOPTrue16Info {
#define GET_FP4FP8DstByteSelTable_IMPL
struct DPMACCInstructionInfo {
- uint16_t Opcode;
+ uint32_t Opcode;
bool IsDPMACCInstruction;
};
struct FP4FP8DstByteSelInfo {
- uint16_t Opcode;
+ uint32_t Opcode;
bool HasFP8DstByteSel;
bool HasFP4DstByteSel;
};
@@ -808,7 +808,7 @@ unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc) {
// Wrapper for Tablegen'd function. enum Subtarget is not defined in any
// header files, so we need to wrap it in a function that takes unsigned
// instead.
-int getMCOpcode(uint16_t Opcode, unsigned Gen) {
+int getMCOpcode(uint32_t Opcode, unsigned Gen) {
return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
}
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index 0ecec79d08a38..1850e0fe59625 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -98,7 +98,7 @@ struct GcnBufferFormatInfo {
};
struct MAIInstInfo {
- uint16_t Opcode;
+ uint32_t Opcode;
bool is_dgemm;
bool is_gfx940_xdl;
};
@@ -121,7 +121,7 @@ struct True16D16Info {
};
struct WMMAInstInfo {
- uint16_t Opcode;
+ uint32_t Opcode;
bool is_wmma_xdl;
};
@@ -416,7 +416,7 @@ inline bool hasNamedOperand(uint64_t Opcode, OpName NamedIdx) {
}
LLVM_READONLY
-int getSOPPWithRelaxation(uint16_t Opcode);
+int getSOPPWithRelaxation(uint32_t Opcode);
struct MIMGBaseOpcodeInfo {
MIMGBaseOpcode BaseOpcode;
@@ -522,7 +522,7 @@ unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
bool IsG16Supported);
struct MIMGInfo {
- uint16_t Opcode;
+ uint32_t Opcode;
uint16_t BaseOpcode;
uint8_t MIMGEncoding;
uint8_t VDataDwords;
@@ -646,7 +646,7 @@ const GcnBufferFormatInfo *getGcnBufferFormatInfo(uint8_t Format,
const MCSubtargetInfo &STI);
LLVM_READONLY
-int getMCOpcode(uint16_t Opcode, unsigned Gen);
+int getMCOpcode(uint32_t Opcode, unsigned Gen);
LLVM_READONLY
unsigned getVOPDOpcode(unsigned Opc, bool VOPD3);
diff --git a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
index a942d2f9c7e8e..402f852a1ca70 100644
--- a/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
+++ b/llvm/lib/Target/PowerPC/PPCHazardRecognizers.cpp
@@ -78,7 +78,7 @@ bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) {
}
// FIXME: Remove this when we don't need this:
-namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint16_t); } }
+namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint32_t); } }
// FIXME: A lot of code in PPCDispatchGroupSBHazardRecognizer is P7 specific.
diff --git a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
index 7e3ea606087b3..1eb2539353e46 100644
--- a/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
+++ b/llvm/lib/Target/PowerPC/PPCVSXFMAMutate.cpp
@@ -47,7 +47,7 @@ static cl::opt<bool> DisableVSXFMAMutate(
#define DEBUG_TYPE "ppc-vsx-fma-mutate"
namespace llvm { namespace PPC {
- int getAltVSXFMAOpcode(uint16_t Opcode);
+ int getAltVSXFMAOpcode(uint32_t Opcode);
} }
namespace {
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
index 29ae9e0ed80e7..4653978d954f4 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.h
@@ -159,8 +159,8 @@ enum FusedCompareType {
} // end namespace SystemZII
namespace SystemZ {
-int getTwoOperandOpcode(uint16_t Opcode);
-int getTargetMemOpcode(uint16_t Opcode);
+int getTwoOperandOpcode(uint32_t Opcode);
+int getTargetMemOpcode(uint32_t Opcode);
// Return a version of comparison CC mask CCMask in which the LT and GT
// actions are swapped.
diff --git a/llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h b/llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h
index 741cc002f9e25..ad40e722c90ec 100644
--- a/llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h
+++ b/llvm/lib/Target/WebAssembly/TargetInfo/WebAssemblyTargetInfo.h
@@ -23,9 +23,9 @@ Target &getTheWebAssemblyTarget64();
namespace WebAssembly {
-int getStackOpcode(unsigned short Opcode);
-int getRegisterOpcode(unsigned short Opcode);
-int getWasm64Opcode(unsigned short Opcode);
+int getStackOpcode(unsigned int Opcode);
+int getRegisterOpcode(unsigned int Opcode);
+int getWasm64Opcode(unsigned int Opcode);
} // namespace WebAssembly
diff --git a/llvm/test/TableGen/get-named-operand-idx.td b/llvm/test/TableGen/get-named-operand-idx.td
index 7982822c0a895..5e6a9859f3603 100644
--- a/llvm/test/TableGen/get-named-operand-idx.td
+++ b/llvm/test/TableGen/get-named-operand-idx.td
@@ -64,8 +64,8 @@ defm : RemapAllTargetPseudoPointerOperands<RegClass>;
// CHECK-NEXT: NUM_OPERAND_NAMES = 5,
// CHECK-NEXT: }; // enum class OpName
// CHECK-EMPTY:
-// CHECK-NEXT: LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name);
-// CHECK-NEXT: LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx);
+// CHECK-NEXT: LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name);
+// CHECK-NEXT: LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx);
// CHECK-EMPTY:
// CHECK-NEXT: } // namespace llvm::MyNamespace
// CHECK-EMPTY:
@@ -76,7 +76,7 @@ defm : RemapAllTargetPseudoPointerOperands<RegClass>;
// CHECK-EMPTY:
// CHECK-NEXT: namespace llvm::MyNamespace {
// CHECK-EMPTY:
-// CHECK-NEXT: LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint16_t Opcode) {
+// CHECK-NEXT: LLVM_READONLY static uint8_t getInstructionIndexForOpLookup(uint32_t Opcode) {
// CHECK-NEXT: static constexpr uint8_t InstructionIndex[] = {
// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
// CHECK-NEXT: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -102,7 +102,7 @@ defm : RemapAllTargetPseudoPointerOperands<RegClass>;
// CHECK-NEXT: };
// CHECK-NEXT: return InstructionIndex[Opcode];
// CHECK-NEXT: }
-// CHECK-NEXT: LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName Name) {
+// CHECK-NEXT: LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName Name) {
// CHECK-NEXT: assert(Name != OpName::NUM_OPERAND_NAMES);
// CHECK-NEXT: static constexpr int8_t OperandMap[][5] = {
// CHECK-NEXT: {-1, -1, -1, -1, -1, },
@@ -112,7 +112,7 @@ defm : RemapAllTargetPseudoPointerOperands<RegClass>;
// CHECK-NEXT: unsigned InstrIdx = getInstructionIndexForOpLookup(Opcode);
// CHECK-NEXT: return OperandMap[InstrIdx][(unsigned)Name];
// CHECK-NEXT: }
-// CHECK-NEXT: LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx) {
+// CHECK-NEXT: LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx) {
// CHECK-NEXT: assert(Idx >= 0 && Idx < 3);
// CHECK-NEXT: static constexpr OpName OperandMap[][3] = {
// CHECK-NEXT: {OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, OpName::NUM_OPERAND_NAMES, },
diff --git a/llvm/utils/TableGen/AsmMatcherEmitter.cpp b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
index 5610123f3323a..00f5c033cf52f 100644
--- a/llvm/utils/TableGen/AsmMatcherEmitter.cpp
+++ b/llvm/utils/TableGen/AsmMatcherEmitter.cpp
@@ -3609,7 +3609,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) {
OS << "namespace {\n";
OS << " struct MatchEntry {\n";
OS << " " << getMinimalTypeForRange(MaxMnemonicIndex) << " Mnemonic;\n";
- OS << " uint16_t Opcode;\n";
+ OS << " uint32_t Opcode;\n";
OS << " " << getMinimalTypeForRange(NumConverters) << " ConvertFn;\n";
OS << " " << getMinimalTypeForRange(FeatureBitsets.size())
<< " RequiredFeaturesIdx;\n";
diff --git a/llvm/utils/TableGen/CodeGenMapTable.cpp b/llvm/utils/TableGen/CodeGenMapTable.cpp
index 35ec495b93ba2..1bed6001957b1 100644
--- a/llvm/utils/TableGen/CodeGenMapTable.cpp
+++ b/llvm/utils/TableGen/CodeGenMapTable.cpp
@@ -474,7 +474,7 @@ void MapTableEmitter::emitTablesWithFunc(raw_ostream &OS) {
const ListInit *ColFields = InstrMapDesc.getColFields();
ArrayRef<const ListInit *> ValueCols = InstrMapDesc.getValueCols();
OS << "// " << InstrMapDesc.getName() << "\nLLVM_READONLY\n";
- OS << "int " << InstrMapDesc.getName() << "(uint16_t Opcode";
+ OS << "int " << InstrMapDesc.getName() << "(uint32_t Opcode";
if (ValueCols.size() > 1) {
for (const Init *CF : ColFields->getElements()) {
std::string ColName = CF->getAsUnquotedString();
diff --git a/llvm/utils/TableGen/InstrInfoEmitter.cpp b/llvm/utils/TableGen/InstrInfoEmitter.cpp
index 8442ad0dc0edd..08526cc2a72bf 100644
--- a/llvm/utils/TableGen/InstrInfoEmitter.cpp
+++ b/llvm/utils/TableGen/InstrInfoEmitter.cpp
@@ -261,7 +261,7 @@ static void emitGetInstructionIndexForOpLookup(
ArrayRef<unsigned> InstructionIndex) {
StringRef Type = OperandMap.size() <= UINT8_MAX + 1 ? "uint8_t" : "uint16_t";
OS << "LLVM_READONLY static " << Type
- << " getInstructionIndexForOpLookup(uint16_t Opcode) {\n"
+ << " getInstructionIndexForOpLookup(uint32_t Opcode) {\n"
" static constexpr "
<< Type << " InstructionIndex[] = {";
for (auto [TableIndex, Entry] : enumerate(InstructionIndex))
@@ -275,7 +275,7 @@ static void
emitGetNamedOperandIdx(raw_ostream &OS,
const MapVector<SmallVector<int>, unsigned> &OperandMap,
unsigned MaxOperandNo, unsigned NumOperandNames) {
- OS << "LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName "
+ OS << "LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName "
"Name) {\n";
OS << " assert(Name != OpName::NUM_OPERAND_NAMES);\n";
if (!NumOperandNames) {
@@ -307,7 +307,7 @@ emitGetOperandIdxName(raw_ostream &OS,
const MapVector<StringRef, unsigned> &OperandNameToID,
const MapVector<SmallVector<int>, unsigned> &OperandMap,
unsigned MaxNumOperands, unsigned NumOperandNames) {
- OS << "LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t Idx) "
+ OS << "LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t Idx) "
"{\n";
OS << " assert(Idx >= 0 && Idx < " << MaxNumOperands << ");\n";
if (!MaxNumOperands) {
@@ -347,11 +347,11 @@ emitGetOperandIdxName(raw_ostream &OS,
/// - An enum in the llvm::TargetNamespace::OpName namespace, with one entry
/// for each operand name.
/// - A 2-dimensional table for mapping OpName enum values to operand indices.
-/// - A function called getNamedOperandIdx(uint16_t Opcode, OpName Name)
+/// - A function called getNamedOperandIdx(uint32_t Opcode, OpName Name)
/// for looking up the operand index for an instruction, given a value from
/// OpName enum
/// - A 2-dimensional table for mapping operand indices to OpName enum values.
-/// - A function called getOperandIdxName(uint16_t Opcode, int16_t Idx)
+/// - A function called getOperandIdxName(uint32_t Opcode, int16_t Idx)
/// for looking up the OpName enum for an instruction, given the operand
/// index. This is the inverse of getNamedOperandIdx().
///
@@ -414,9 +414,9 @@ void InstrInfoEmitter::emitOperandNameMappings(
OS << " NUM_OPERAND_NAMES = " << NumOperandNames << ",\n";
OS << "}; // enum class OpName\n\n";
- OS << "LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, OpName "
+ OS << "LLVM_READONLY int16_t getNamedOperandIdx(uint32_t Opcode, OpName "
"Name);\n";
- OS << "LLVM_READONLY OpName getOperandIdxName(uint16_t Opcode, int16_t "
+ OS << "LLVM_READONLY OpName getOperandIdxName(uint32_t Opcode, int16_t "
"Idx);\n";
}
@@ -476,7 +476,7 @@ void InstrInfoEmitter::emitOperandTypeMappings(
IfDefEmitter IfDef(OS, "GET_INSTRINFO_OPERAND_TYPE");
NamespaceEmitter NS(OS, ("llvm::" + Namespace).str());
OS << "LLVM_READONLY\n";
- OS << "static int getOperandType(uint16_t Opcode, uint16_t OpIdx) {\n";
+ OS << "static int getOperandType(uint32_t Opcode, uint16_t OpIdx) {\n";
auto getInstrName = [&](int I) -> StringRef {
return NumberedInstructions[I]->getName();
};
@@ -604,7 +604,7 @@ void InstrInfoEmitter::emitLogicalOperandSizeMappings(
IfDefEmitter IfDef(OS, "GET_INSTRINFO_LOGICAL_OPERAND_SIZE_MAP");
NamespaceEmitter NS(OS, ("llvm::" + Namespace).str());
OS << "LLVM_READONLY static unsigned\n";
- OS << "getLogicalOperandSize(uint16_t Opcode, uint16_t LogicalOpIdx) {\n";
+ OS << "getLogicalOperandSize(uint32_t Opcode, uint16_t LogicalOpIdx) {\n";
if (!InstMap.empty()) {
std::vector<const std::vector<unsigned> *> LogicalOpSizeList(
LogicalOpSizeMap.size());
@@ -644,7 +644,7 @@ void InstrInfoEmitter::emitLogicalOperandSizeMappings(
OS << "}\n";
OS << "LLVM_READONLY static inline unsigned\n";
- OS << "getLogicalOperandIdx(uint16_t Opcode, uint16_t LogicalOpIdx) {\n";
+ OS << "getLogicalOperandIdx(uint32_t Opcode, uint16_t LogicalOpIdx) {\n";
OS << " auto S = 0U;\n";
OS << " for (auto i = 0U; i < LogicalOpIdx; ++i)\n";
OS << " S += getLogicalOperandSize(Opcode, i);\n";
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