[llvm] [RISCV] Use RISCVWidth in interface for vector load/store classes in RISCVInstrFormatsV.td. NFC (PR #179348)
Pengcheng Wang via llvm-commits
llvm-commits at lists.llvm.org
Tue Feb 3 00:07:38 PST 2026
https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/179348
>From c3f1a6420b4d1e5541bca4188c1a50df7af138cf Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 2 Feb 2026 13:05:58 -0800
Subject: [PATCH 1/3] [RISCV] Add common base classes for loads/stores in
RISCVInstrFormatsV.td. NFC
Only bits 24-20 have a different meaning between the different
loads and stores, vs2, rs2, or lumop/sumop.
---
llvm/lib/Target/RISCV/RISCVInstrFormatsV.td | 96 ++++++---------------
1 file changed, 28 insertions(+), 68 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
index a4dfec512899f..79a5e893c8422 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
@@ -162,9 +162,8 @@ class RVInstVUnaryRd<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
let RVVConstraint = NoConstraint;
}
-class RVInstVLU<bits<3> nf, bit mew, RISCVLUMOP lumop,
- bits<3> width, dag outs, dag ins, string opcodestr,
- string argstr>
+class RVInstVLoadBase<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
+ dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs1;
bits<5> vd;
@@ -172,9 +171,9 @@ class RVInstVLU<bits<3> nf, bit mew, RISCVLUMOP lumop,
let Inst{31-29} = nf;
let Inst{28} = mew;
- let Inst{27-26} = MOPLDUnitStride.Value;
+ let Inst{27-26} = mop.Value;
let Inst{25} = vm;
- let Inst{24-20} = lumop.Value;
+ // Inst{24-20} provided by subclasses
let Inst{19-15} = rs1;
let Inst{14-12} = width;
let Inst{11-7} = vd;
@@ -184,53 +183,32 @@ class RVInstVLU<bits<3> nf, bit mew, RISCVLUMOP lumop,
let RVVConstraint = VMConstraint;
}
+class RVInstVLU<bits<3> nf, bit mew, RISCVLUMOP lumop, bits<3> width, dag outs,
+ dag ins, string opcodestr, string argstr>
+ : RVInstVLoadBase<nf, mew, MOPLDUnitStride, width, outs, ins, opcodestr,
+ argstr> {
+ let Inst{24-20} = lumop.Value;
+}
+
class RVInstVLS<bits<3> nf, bit mew, bits<3> width,
dag outs, dag ins, string opcodestr, string argstr>
- : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ : RVInstVLoadBase<nf, mew, MOPLDStrided, width, outs, ins, opcodestr,
+ argstr> {
bits<5> rs2;
- bits<5> rs1;
- bits<5> vd;
- bit vm;
- let Inst{31-29} = nf;
- let Inst{28} = mew;
- let Inst{27-26} = MOPLDStrided.Value;
- let Inst{25} = vm;
let Inst{24-20} = rs2;
- let Inst{19-15} = rs1;
- let Inst{14-12} = width;
- let Inst{11-7} = vd;
- let Inst{6-0} = OPC_LOAD_FP.Value;
-
- let Uses = [VL, VTYPE];
- let RVVConstraint = VMConstraint;
}
class RVInstVLX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
dag outs, dag ins, string opcodestr, string argstr>
- : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ : RVInstVLoadBase<nf, mew, mop, width, outs, ins, opcodestr, argstr> {
bits<5> vs2;
- bits<5> rs1;
- bits<5> vd;
- bit vm;
- let Inst{31-29} = nf;
- let Inst{28} = mew;
- let Inst{27-26} = mop.Value;
- let Inst{25} = vm;
let Inst{24-20} = vs2;
- let Inst{19-15} = rs1;
- let Inst{14-12} = width;
- let Inst{11-7} = vd;
- let Inst{6-0} = OPC_LOAD_FP.Value;
-
- let Uses = [VL, VTYPE];
- let RVVConstraint = VMConstraint;
}
-class RVInstVSU<bits<3> nf, bit mew, RISCVSUMOP sumop,
- bits<3> width, dag outs, dag ins, string opcodestr,
- string argstr>
+class RVInstVStoreBase<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
+ dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs1;
bits<5> vs3;
@@ -238,9 +216,9 @@ class RVInstVSU<bits<3> nf, bit mew, RISCVSUMOP sumop,
let Inst{31-29} = nf;
let Inst{28} = mew;
- let Inst{27-26} = MOPSTUnitStride.Value;
+ let Inst{27-26} = mop.Value;
let Inst{25} = vm;
- let Inst{24-20} = sumop.Value;
+ // Inst{24-20} provided by subclasses
let Inst{19-15} = rs1;
let Inst{14-12} = width;
let Inst{11-7} = vs3;
@@ -249,44 +227,26 @@ class RVInstVSU<bits<3> nf, bit mew, RISCVSUMOP sumop,
let Uses = [VL, VTYPE];
}
+class RVInstVSU<bits<3> nf, bit mew, RISCVSUMOP sumop, bits<3> width, dag outs,
+ dag ins, string opcodestr, string argstr>
+ : RVInstVStoreBase<nf, mew, MOPSTUnitStride, width, outs, ins, opcodestr,
+ argstr> {
+ let Inst{24-20} = sumop.Value;
+}
+
class RVInstVSS<bits<3> nf, bit mew, bits<3> width,
dag outs, dag ins, string opcodestr, string argstr>
- : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ : RVInstVStoreBase<nf, mew, MOPSTStrided, width, outs, ins, opcodestr,
+ argstr> {
bits<5> rs2;
- bits<5> rs1;
- bits<5> vs3;
- bit vm;
- let Inst{31-29} = nf;
- let Inst{28} = mew;
- let Inst{27-26} = MOPSTStrided.Value;
- let Inst{25} = vm;
let Inst{24-20} = rs2;
- let Inst{19-15} = rs1;
- let Inst{14-12} = width;
- let Inst{11-7} = vs3;
- let Inst{6-0} = OPC_STORE_FP.Value;
-
- let Uses = [VL, VTYPE];
}
class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
dag outs, dag ins, string opcodestr, string argstr>
- : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ : RVInstVStoreBase<nf, mew, mop, width, outs, ins, opcodestr, argstr> {
bits<5> vs2;
- bits<5> rs1;
- bits<5> vs3;
- bit vm;
- let Inst{31-29} = nf;
- let Inst{28} = mew;
- let Inst{27-26} = mop.Value;
- let Inst{25} = vm;
let Inst{24-20} = vs2;
- let Inst{19-15} = rs1;
- let Inst{14-12} = width;
- let Inst{11-7} = vs3;
- let Inst{6-0} = OPC_STORE_FP.Value;
-
- let Uses = [VL, VTYPE];
}
>From 83e579056033e8567dd310918eee62079b1a10c5 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Mon, 2 Feb 2026 14:05:55 -0800
Subject: [PATCH 2/3] [RISCV] Use RISCVWidth in interface for vector load/store
classes in RISCVInstrFormatsV.td. NFC
This avoids repeating the splitting into mew/width in multiple places.
Stacked on #179329
---
llvm/lib/Target/RISCV/RISCVInstrFormatsV.td | 47 +++++++++---------
llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 54 +++++++++------------
2 files changed, 46 insertions(+), 55 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
index 79a5e893c8422..8aa3fb341e3b4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
@@ -162,7 +162,7 @@ class RVInstVUnaryRd<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
let RVVConstraint = NoConstraint;
}
-class RVInstVLoadBase<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
+class RVInstVLoadBase<bits<3> nf, RISCVWidth width, RISCVMOP mop,
dag outs, dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs1;
@@ -170,12 +170,12 @@ class RVInstVLoadBase<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
bit vm;
let Inst{31-29} = nf;
- let Inst{28} = mew;
+ let Inst{28} = width.Value{3};
let Inst{27-26} = mop.Value;
let Inst{25} = vm;
// Inst{24-20} provided by subclasses
let Inst{19-15} = rs1;
- let Inst{14-12} = width;
+ let Inst{14-12} = width.Value{2-0};
let Inst{11-7} = vd;
let Inst{6-0} = OPC_LOAD_FP.Value;
@@ -183,69 +183,68 @@ class RVInstVLoadBase<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
let RVVConstraint = VMConstraint;
}
-class RVInstVLU<bits<3> nf, bit mew, RISCVLUMOP lumop, bits<3> width, dag outs,
+class RVInstVLU<bits<3> nf, RISCVWidth width, RISCVLUMOP lumop, dag outs,
dag ins, string opcodestr, string argstr>
- : RVInstVLoadBase<nf, mew, MOPLDUnitStride, width, outs, ins, opcodestr,
+ : RVInstVLoadBase<nf, width, MOPLDUnitStride, outs, ins, opcodestr,
argstr> {
let Inst{24-20} = lumop.Value;
}
-class RVInstVLS<bits<3> nf, bit mew, bits<3> width,
- dag outs, dag ins, string opcodestr, string argstr>
- : RVInstVLoadBase<nf, mew, MOPLDStrided, width, outs, ins, opcodestr,
- argstr> {
+class RVInstVLS<bits<3> nf, RISCVWidth width, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInstVLoadBase<nf, width, MOPLDStrided, outs, ins, opcodestr, argstr> {
bits<5> rs2;
let Inst{24-20} = rs2;
}
-class RVInstVLX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
- dag outs, dag ins, string opcodestr, string argstr>
- : RVInstVLoadBase<nf, mew, mop, width, outs, ins, opcodestr, argstr> {
+class RVInstVLX<bits<3> nf, RISCVWidth width, RISCVMOP mop, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInstVLoadBase<nf, width, mop, outs, ins, opcodestr, argstr> {
bits<5> vs2;
let Inst{24-20} = vs2;
}
-class RVInstVStoreBase<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
- dag outs, dag ins, string opcodestr, string argstr>
+class RVInstVStoreBase<bits<3> nf, RISCVWidth width, RISCVMOP mop, dag outs,
+ dag ins, string opcodestr, string argstr>
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
bits<5> rs1;
bits<5> vs3;
bit vm;
let Inst{31-29} = nf;
- let Inst{28} = mew;
+ let Inst{28} = width.Value{3};
let Inst{27-26} = mop.Value;
let Inst{25} = vm;
// Inst{24-20} provided by subclasses
let Inst{19-15} = rs1;
- let Inst{14-12} = width;
+ let Inst{14-12} = width.Value{2-0};
let Inst{11-7} = vs3;
let Inst{6-0} = OPC_STORE_FP.Value;
let Uses = [VL, VTYPE];
}
-class RVInstVSU<bits<3> nf, bit mew, RISCVSUMOP sumop, bits<3> width, dag outs,
+class RVInstVSU<bits<3> nf, RISCVWidth width, RISCVSUMOP sumop, dag outs,
dag ins, string opcodestr, string argstr>
- : RVInstVStoreBase<nf, mew, MOPSTUnitStride, width, outs, ins, opcodestr,
+ : RVInstVStoreBase<nf, width, MOPSTUnitStride, outs, ins, opcodestr,
argstr> {
let Inst{24-20} = sumop.Value;
}
-class RVInstVSS<bits<3> nf, bit mew, bits<3> width,
- dag outs, dag ins, string opcodestr, string argstr>
- : RVInstVStoreBase<nf, mew, MOPSTStrided, width, outs, ins, opcodestr,
+class RVInstVSS<bits<3> nf, RISCVWidth width, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInstVStoreBase<nf, width, MOPSTStrided, outs, ins, opcodestr,
argstr> {
bits<5> rs2;
let Inst{24-20} = rs2;
}
-class RVInstVSX<bits<3> nf, bit mew, RISCVMOP mop, bits<3> width,
- dag outs, dag ins, string opcodestr, string argstr>
- : RVInstVStoreBase<nf, mew, mop, width, outs, ins, opcodestr, argstr> {
+class RVInstVSX<bits<3> nf, RISCVWidth width, RISCVMOP mop, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInstVStoreBase<nf, width, mop, outs, ins, opcodestr, argstr> {
bits<5> vs2;
let Inst{24-20} = vs2;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index e674a48957b43..00125e08fb5a1 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -344,70 +344,62 @@ def RISCVBaseVXMemOpTable : GenericTable {
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
// unit-stride load vd, (rs1), vm
class VUnitStrideLoad<RISCVWidth width, string opcodestr>
- : RVInstVLU<0b000, width.Value{3}, LUMOPUnitStride, width.Value{2-0},
+ : RVInstVLU<0b000, width, LUMOPUnitStride,
(outs VR:$vd),
(ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">;
let vm = 1, RVVConstraint = NoConstraint in {
// unit-stride whole register load vl<nf>r.v vd, (rs1)
class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr, RegisterClass VRC>
- : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideWholeReg,
- width.Value{2-0}, (outs VRC:$vd), (ins GPRMemZeroOffset:$rs1),
+ : RVInstVLU<nf, width, LUMOPUnitStrideWholeReg, (outs VRC:$vd),
+ (ins GPRMemZeroOffset:$rs1),
opcodestr, "$vd, $rs1"> {
let Uses = [];
}
// unit-stride mask load vd, (rs1)
class VUnitStrideLoadMask<string opcodestr>
- : RVInstVLU<0b000, LSWidth8.Value{3}, LUMOPUnitStrideMask, LSWidth8.Value{2-0},
- (outs VR:$vd),
+ : RVInstVLU<0b000, LSWidth8, LUMOPUnitStrideMask, (outs VR:$vd),
(ins GPRMemZeroOffset:$rs1), opcodestr, "$vd, $rs1">;
} // vm = 1, RVVConstraint = NoConstraint
// unit-stride fault-only-first load vd, (rs1), vm
class VUnitStrideLoadFF<RISCVWidth width, string opcodestr>
- : RVInstVLU<0b000, width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0},
- (outs VR:$vd),
+ : RVInstVLU<0b000, width, LUMOPUnitStrideFF, (outs VR:$vd),
(ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">;
// strided load vd, (rs1), rs2, vm
class VStridedLoad<RISCVWidth width, string opcodestr>
- : RVInstVLS<0b000, width.Value{3}, width.Value{2-0},
- (outs VR:$vd),
+ : RVInstVLS<0b000, width, (outs VR:$vd),
(ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
"$vd, $rs1, $rs2$vm">;
// indexed load vd, (rs1), vs2, vm
class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
- : RVInstVLX<0b000, width.Value{3}, mop, width.Value{2-0},
- (outs VR:$vd),
+ : RVInstVLX<0b000, width, mop, (outs VR:$vd),
(ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
"$vd, $rs1, $vs2$vm">;
// unit-stride segment load vd, (rs1), vm
class VUnitStrideSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
- : RVInstVLU<nf, width.Value{3}, LUMOPUnitStride, width.Value{2-0},
- (outs VR:$vd),
+ : RVInstVLU<nf, width, LUMOPUnitStride, (outs VR:$vd),
(ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">;
// segment fault-only-first load vd, (rs1), vm
class VUnitStrideSegmentLoadFF<bits<3> nf, RISCVWidth width, string opcodestr>
- : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideFF, width.Value{2-0},
- (outs VR:$vd),
+ : RVInstVLU<nf, width, LUMOPUnitStrideFF, (outs VR:$vd),
(ins GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr, "$vd, ${rs1}$vm">;
// strided segment load vd, (rs1), rs2, vm
class VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
- : RVInstVLS<nf, width.Value{3}, width.Value{2-0},
- (outs VR:$vd),
+ : RVInstVLS<nf, width, (outs VR:$vd),
(ins GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
"$vd, $rs1, $rs2$vm">;
// indexed segment load vd, (rs1), vs2, vm
class VIndexedSegmentLoad<bits<3> nf, RISCVMOP mop, RISCVWidth width,
string opcodestr>
- : RVInstVLX<nf, width.Value{3}, mop, width.Value{2-0},
- (outs VR:$vd),
+ : RVInstVLX<nf, width, mop, (outs VR:$vd),
(ins GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm), opcodestr,
"$vd, $rs1, $vs2$vm">;
} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
@@ -415,54 +407,54 @@ class VIndexedSegmentLoad<bits<3> nf, RISCVMOP mop, RISCVWidth width,
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
// unit-stride store vd, vs3, (rs1), vm
class VUnitStrideStore<RISCVWidth width, string opcodestr>
- : RVInstVSU<0b000, width.Value{3}, SUMOPUnitStride, width.Value{2-0},
- (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr,
+ : RVInstVSU<0b000, width, SUMOPUnitStride, (outs),
+ (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr,
"$vs3, ${rs1}$vm">;
let vm = 1 in {
// vs<nf>r.v vd, (rs1)
class VWholeStore<bits<3> nf, string opcodestr, RegisterClass VRC>
- : RVInstVSU<nf, 0, SUMOPUnitStrideWholeReg,
- 0b000, (outs), (ins VRC:$vs3, GPRMemZeroOffset:$rs1),
+ : RVInstVSU<nf, LSWidth8, SUMOPUnitStrideWholeReg, (outs),
+ (ins VRC:$vs3, GPRMemZeroOffset:$rs1),
opcodestr, "$vs3, $rs1"> {
let Uses = [];
}
// unit-stride mask store vd, vs3, (rs1)
class VUnitStrideStoreMask<string opcodestr>
- : RVInstVSU<0b000, LSWidth8.Value{3}, SUMOPUnitStrideMask, LSWidth8.Value{2-0},
- (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1), opcodestr,
+ : RVInstVSU<0b000, LSWidth8, SUMOPUnitStrideMask, (outs),
+ (ins VR:$vs3, GPRMemZeroOffset:$rs1), opcodestr,
"$vs3, $rs1">;
} // vm = 1
// strided store vd, vs3, (rs1), rs2, vm
class VStridedStore<RISCVWidth width, string opcodestr>
- : RVInstVSS<0b000, width.Value{3}, width.Value{2-0}, (outs),
+ : RVInstVSS<0b000, width, (outs),
(ins VR:$vs3, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
opcodestr, "$vs3, $rs1, $rs2$vm">;
// indexed store vd, vs3, (rs1), vs2, vm
class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
- : RVInstVSX<0b000, width.Value{3}, mop, width.Value{2-0}, (outs),
+ : RVInstVSX<0b000, width, mop, (outs),
(ins VR:$vs3, GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm),
opcodestr, "$vs3, $rs1, $vs2$vm">;
// segment store vd, vs3, (rs1), vm
class VUnitStrideSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
- : RVInstVSU<nf, width.Value{3}, SUMOPUnitStride, width.Value{2-0},
- (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr,
+ : RVInstVSU<nf, width, SUMOPUnitStride, (outs),
+ (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr,
"$vs3, ${rs1}$vm">;
// segment store vd, vs3, (rs1), rs2, vm
class VStridedSegmentStore<bits<3> nf, RISCVWidth width, string opcodestr>
- : RVInstVSS<nf, width.Value{3}, width.Value{2-0}, (outs),
+ : RVInstVSS<nf, width, (outs),
(ins VR:$vs3, GPRMemZeroOffset:$rs1, GPR:$rs2, VMaskOp:$vm),
opcodestr, "$vs3, $rs1, $rs2$vm">;
// segment store vd, vs3, (rs1), vs2, vm
class VIndexedSegmentStore<bits<3> nf, RISCVMOP mop, RISCVWidth width,
string opcodestr>
- : RVInstVSX<nf, width.Value{3}, mop, width.Value{2-0}, (outs),
+ : RVInstVSX<nf, width, mop, (outs),
(ins VR:$vs3, GPRMemZeroOffset:$rs1, VR:$vs2, VMaskOp:$vm),
opcodestr, "$vs3, $rs1, $vs2$vm">;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
>From 6e9250b93aface4922cc238e875205e0044624f7 Mon Sep 17 00:00:00 2001
From: Pengcheng Wang <wangpengcheng.pp at bytedance.com>
Date: Tue, 3 Feb 2026 16:07:29 +0800
Subject: [PATCH 3/3] Add comma
---
llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
index 5b3a5defc4a3c..9374b6794235b 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -420,7 +420,7 @@ class VUnitStrideStore<RISCVWidth width, string opcodestr>
let vm = 1 in {
// vs<lmul>r.v vd, (rs1)
class VWholeStore<int lmul, string opcodestr, RegisterClass VRC>
- : RVInstVSU<!sub(lmul, 1), LSWidth8, SUMOPUnitStrideWholeReg, (outs)
+ : RVInstVSU<!sub(lmul, 1), LSWidth8, SUMOPUnitStrideWholeReg, (outs),
(ins VRC:$vs3, GPRMemZeroOffset:$rs1),
opcodestr, "$vs3, $rs1"> {
assert !and(!ge(lmul, 1), !le(lmul, 8)), "lmul must be 1-8";
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