[llvm] [RISCV] Use RISCVWidth in interface for vector load/store classes in RISCVInstrFormatsV.td. NFC (PR #179348)

[Pengcheng Wang via llvm-commits]

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@@ -421,15 +413,15 @@ class VIndexedSegmentLoad<int nfields, RISCVMOP mop, RISCVWidth width,
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
 // unit-stride store vd, vs3, (rs1), vm
 class VUnitStrideStore<RISCVWidth width, string opcodestr>
-    : RVInstVSU<0b000, width.Value{3}, SUMOPUnitStride, width.Value{2-0},
-                (outs), (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr,
+    : RVInstVSU<0b000, width, SUMOPUnitStride, (outs),
+                (ins VR:$vs3, GPRMemZeroOffset:$rs1, VMaskOp:$vm), opcodestr,
                 "$vs3, ${rs1}$vm">;
 
 let vm = 1 in {
 // vs<lmul>r.v vd, (rs1)
 class VWholeStore<int lmul, string opcodestr, RegisterClass VRC>
-    : RVInstVSU<!sub(lmul, 1), 0, SUMOPUnitStrideWholeReg,
-                0b000, (outs), (ins VRC:$vs3, GPRMemZeroOffset:$rs1),
+    : RVInstVSU<!sub(lmul, 1), LSWidth8, SUMOPUnitStrideWholeReg, (outs)
----------------
wangpc-pp wrote:

```suggestion
    : RVInstVSU<!sub(lmul, 1), LSWidth8, SUMOPUnitStrideWholeReg, (outs),
```

https://github.com/llvm/llvm-project/pull/179348