[llvm] [AMDGPU][SIRegisterInfo] Fix maxoffset calculation in buildSpillLoadStore (PR #179182)

[Christudasan Devadasan via llvm-commits]

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@@ -1549,7 +1549,10 @@ void SIRegisterInfo::buildSpillLoadStore(
   int64_t Offset = InstOffset + MFI.getObjectOffset(Index);
   int64_t MaterializedOffset = Offset;
 
-  int64_t MaxOffset = Offset + Size + RemSize - EltSize;
+  // Maxoffset is the starting offset for the last chunk to be spilled.
+  // In case of non-zero remainder element, max offset will be the
+  // last address(offset + Size) after spilling  all the EltSize chunks.
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cdevadas wrote:

// In case of non-zero remainder element, max offset will be the
  // last address(offset + Size) after spilling  all the EltSize chunks.

> Instead of 'max offset will be the last address after spilling all the EltSize chunks', shouldn't this be 'max offset will be the start address for the last EltSize chunk'?

https://github.com/llvm/llvm-project/pull/179182