[llvm] [AMDGPU][SIRegisterInfo] Fix maxoffset calculation in buildSpillLoadStore (PR #179182)

[Christudasan Devadasan via llvm-commits]

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@@ -0,0 +1,34 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
+# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 -verify-machineinstrs -simplify-mir -amdgpu-spill-vgpr-to-agpr=0 -run-pass=prologepilog -o - %s | FileCheck %s
+
+# Test that the PEI pass does correct calculations for Maxoffset in case of
+# spill instructions. Must emit offset within 13 bit signed number range.
+
+---
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cdevadas wrote:

@abhigargrepo rename this test to match the other test name and then add a suffix gfx950.

https://github.com/llvm/llvm-project/pull/179182