[llvm] [RISCV][llvm] Support frame index in zilsd optimizer (PR #174073)

[Craig Topper via llvm-commits]

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@@ -347,21 +360,23 @@ bool RISCVPreAllocZilsdOpt::rescheduleOps(
     if (IsLoad) {
       MIB = BuildMI(*MBB, InsertPos, DL, TII->get(RISCV::PseudoLD_RV32_OPT))
                 .addReg(FirstReg, RegState::Define)
-                .addReg(SecondReg, RegState::Define)
-                .addReg(BaseReg)
-                .add(OffsetOp);
+                .addReg(SecondReg, RegState::Define);
       ++NumLDFormed;
       LLVM_DEBUG(dbgs() << "Formed LD: " << *MIB << "\n");
     } else {
       MIB = BuildMI(*MBB, InsertPos, DL, TII->get(RISCV::PseudoSD_RV32_OPT))
                 .addReg(FirstReg)
-                .addReg(SecondReg)
-                .addReg(BaseReg)
-                .add(OffsetOp);
+                .addReg(SecondReg);
       ++NumSDFormed;
       LLVM_DEBUG(dbgs() << "Formed SD: " << *MIB << "\n");
     }
 
+    if (BaseIsReg)
+      MIB = MIB.addReg(BaseReg);
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topperc wrote:

Can we use use `BaseOp.getReg()` here and get rid of the `BaseReg` variable?

https://github.com/llvm/llvm-project/pull/174073