[llvm] [AArch64]SIMD fpcvt codegen for rounding nodes (PR #165546)

[David Green via llvm-commits]

https://github.com/davemgreen approved this pull request.

Thanks LGTM.

> These were added to handle cases like [these](https://godbolt.org/z/Erf5EYo9x), where there is extra unnecessary move. Though I couldn't generate this IR from C source, so maybe there is an issue in frontend preventing rounding intrinsics from being generated in which case I agree this will not help in practice until that is fixed.

I was thinking of things like store_i32(lrint), but wanted store_f32(bitcast(lrint)) then DAG would happily convert it back into store_i32(lrint) by optimizing the store+bitcast together. GISel has a nicer solution for this kind of problem, and I'm hoping it can be made more so in the future.

https://github.com/llvm/llvm-project/pull/165546