[llvm] [AArch64]SIMD fpcvt codegen for rounding nodes (PR #165546)

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Lukacma wrote:

> That does make thinks clearer, thanks. I think the GISel part is the part that worked better, I'm not sure these will do much use in practice as the bitcast will often be optimized away. They don't look incorrect to me though, so long as A and X are the sensible conversions to use.

These were added to handle cases like [these](https://godbolt.org/z/Erf5EYo9x), where there is extra unnecessary move. Though I couldn't generate this IR from C source, so maybe there is an issue in frontend preventing rounding intrinsics from being generated in which case I agree this will not help in practice until that is fixed.

https://github.com/llvm/llvm-project/pull/165546