[llvm] [AArch64] Fix the assertion failure on `RegisterVT == PartVT && "Part… (PR #170632)

[Cheng Lingfei via llvm-commits]

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@@ -0,0 +1,46 @@
+; RUN: llc -mtriple=aarch64--linux-gnu < %s | FileCheck %s
+
+define dso_local void @_Z3fooi(i32 noundef %val) #0 {
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clingfei wrote:

> Note that this test would only be valid in combination with the attribute `vscale_range(2,0)` or `vscale_range(2,2)`, otherwise `<8 x i32>` may not fit in scalable vector register `z1`.

I found there is another assertion failure even with the `vscale_range` when I enabled the `-mattr=+sve`: https://godbolt.org/z/fGvYz168d.

But when the `-mattr=+sve` is not set, the `vscale_range` seems not to affect the test. 


https://github.com/llvm/llvm-project/pull/170632