[llvm] [AArch64] Fix the assertion failure on `RegisterVT == PartVT && "Part… (PR #170632)

[via llvm-commits]

clingfei wrote:

> Hi - high level, what is this expected to do? It looks like it is trying passing a 256bit vector to a register that could be between 128bits and 2048?

I think so. But I am not sure how the test case is generated. Maybe @k-arrows can explain more details. 


https://github.com/llvm/llvm-project/pull/170632