[llvm] [AArch64] Fix the assertion failure on `RegisterVT == PartVT && "Part… (PR #170632)

[David Green via llvm-commits]

davemgreen wrote:

Hi - high level, what is this expected to do? It looks like it is trying passing a 256bit vector to a register that could be between 128bits and 2048?

https://github.com/llvm/llvm-project/pull/170632