[llvm] [RISCV][llvm] Support VFADD, VFSUB, VFMUL codegen for Zvfbfa (PR #170612)

[Luke Lau via llvm-commits]

================
@@ -1090,6 +1091,36 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
         ISD::VECREDUCE_FMINIMUM,
         ISD::VECREDUCE_FMAXIMUM};
 
+    // TODO: support more ops.
----------------
lukel97 wrote:

Just to check, this list should be come smaller over time right? Should the comment say something like

```suggestion
    // TODO: Make more of these ops legal.
```

https://github.com/llvm/llvm-project/pull/170612