[llvm] [RISCV] Use vsetivli instead of `x0,x0` form to retain SEW/LMUL when AVL is imm (PR #169307)

[Luke Lau via llvm-commits]

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@@ -1725,6 +1737,14 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
                 AvailableInfo, OldExit);
 }
 
+bool RISCVInsertVSETVLI::isVLPreserving(const MachineInstr &PrevMI,
+                                        const MachineInstr &MI) const {
+  return MI.getOpcode() == RISCV::PseudoVSETIVLI &&
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lukel97 wrote:

Nit, can we move the `RISCVInstrInfo::isVLPreservingConfig(MI)` check in here? 

https://github.com/llvm/llvm-project/pull/169307