[llvm] [RISCV] Use vsetivli instead of `x0,x0` form to retain SEW/LMUL when AVL is imm (PR #169307)

[Luke Lau via llvm-commits]

https://github.com/lukel97 commented:

I can't comment much on the microarchitecture specifics, but assuming its no worse than x0,x0 then it sounds reasonable if it makes allows us to coalesce more vsetivlis away. 

https://github.com/llvm/llvm-project/pull/169307