[llvm] [RISCV] Implement RVV scheduling model for andes 45 series processor. (PR #167821)

[Min-Yih Hsu via llvm-commits]

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mshockwave wrote:

> (VLEN/SEW)

Should this be VL? both this and indexed load below use Andes45GetCyclesOnePerElement but indexed load writes `VL` in the comment (also I believe Andes45GetCyclesOnePerElement's formula is proportional to VL)

https://github.com/llvm/llvm-project/pull/167821