[llvm] [RISCV] Implement RVV scheduling model for andes 45 series processor. (PR #167821)

[Min-Yih Hsu via llvm-commits]

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mshockwave wrote:

just want to make sure it's intended that rthroughput will be (much) larger than latency in some cases. 
Though latency is usually larger than rthroughput, having the opposite way is also supported in both MachineScheduler and MCA -- just want to double check here.

https://github.com/llvm/llvm-project/pull/167821