[llvm] [RISCV] tt-ascalon-d8 vector scheduling (PR #167066)
Petr Penzin via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 18 00:17:45 PST 2025
https://github.com/ppenzin updated https://github.com/llvm/llvm-project/pull/167066
>From 162020b748089263ed310b99cfbded59e4d9ae79 Mon Sep 17 00:00:00 2001
From: Petr Penzin <ppenzin at tenstorrent.com>
Date: Fri, 7 Nov 2025 18:51:19 -0600
Subject: [PATCH 1/9] [WIP][RISCV] tt-ascalon-d8 vector scheduling
Drive-by: additional tuning knobs.
Partial scheduling model for vector operations.
---
llvm/lib/Target/RISCV/RISCVProcessors.td | 7 +
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 318 +++++++++++++++++-
2 files changed, 319 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index e86431f78f1ba..07f6a38c77897 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -633,6 +633,13 @@ def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
FeatureUnalignedVectorMem]),
[TuneNoDefaultUnroll,
TuneNLogNVRGather,
+ TuneOptimizedNF2SegmentLoadStore,
+ TuneOptimizedNF3SegmentLoadStore,
+ TuneOptimizedNF4SegmentLoadStore,
+ TuneOptimizedNF5SegmentLoadStore,
+ TuneOptimizedNF6SegmentLoadStore,
+ TuneOptimizedNF7SegmentLoadStore,
+ TuneOptimizedNF8SegmentLoadStore,
TuneOptimizedZeroStrideLoad,
TunePostRAScheduler]>;
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index da89e158f9839..973e55b5c53f8 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -8,19 +8,85 @@
//===----------------------------------------------------------------------===//
+class AscalonIsWorstCaseMX<string mx, list<string> MxList> {
+ defvar LLMUL = LargestLMUL<MxList>.r;
+ bit c = !eq(mx, LLMUL);
+}
+
+class AscalonIsWorstCaseMXSEW<string mx, int sew, list<string> MxList,
+ bit isF = 0> {
+ defvar LLMUL = LargestLMUL<MxList>.r;
+ defvar SSEW = SmallestSEW<mx, isF>.r;
+ bit c = !and(!eq(mx, LLMUL), !eq(sew, SSEW));
+}
+
+/// Cycle counts that scale with LMUL with LMUL=1 having the same latency as
+/// fractional LMULs
+class AscalonGetCyclesLMUL<string mx, int base> {
+ int c = !cond(
+ !eq(mx, "M1") : base,
+ !eq(mx, "M2") : !mul(base, 2),
+ !eq(mx, "M4") : !mul(base, 4),
+ !eq(mx, "M8") : !mul(base, 8),
+ !eq(mx, "MF2") : base,
+ !eq(mx, "MF4") : base,
+ !eq(mx, "MF8") : base
+ );
+}
+
+/// Linear LMUL scaling starting from smallest fractional LMUL
+class AscalonGetCyclesLMULFractional<string mx, int base> {
+ int c = !cond(
+ !eq(mx, "MF8") : base,
+ !eq(mx, "MF4") : !mul(base, 2),
+ !eq(mx, "MF2") : !mul(base, 4),
+ !eq(mx, "M1") : !mul(base, 8),
+ !eq(mx, "M2") : !mul(base, 16),
+ !eq(mx, "M4") : !mul(base, 32),
+ !eq(mx, "M8") : !mul(base, 64)
+ );
+}
+
+class AscalonGetCyclesDefault<string mx> {
+ int c = AscalonGetCyclesLMUL<mx, 1>.c;
+}
+
+class AscalonGetCyclesNarrowing<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 4,
+ !eq(mx, "M2") : 8,
+ !eq(mx, "M4") : 16,
+ !eq(mx, "MF2") : 2,
+ !eq(mx, "MF4") : 1,
+ !eq(mx, "MF8") : 1
+ );
+}
+
+
+class AscalonGetCyclesDivOrSqrt<string mx, int sew> {
+ int c = !cond(
+ !eq(sew, 8) : AscalonGetCyclesLMUL<mx, 7>.c, // TODO not valid for fp
+ !eq(sew, 16) : AscalonGetCyclesLMUL<mx, 6>.c,
+ !eq(sew, 32) : AscalonGetCyclesLMUL<mx, 5>.c,
+ !eq(sew, 64) : AscalonGetCyclesLMUL<mx, 8>.c
+ );
+}
+
+//===----------------------------------------------------------------------===//
+
def TTAscalonD8Model : SchedMachineModel {
let IssueWidth = 8; // 8-way decode and dispatch
let MicroOpBufferSize = 256; // 256 micro-op re-order buffer
let LoadLatency = 4; // Optimistic load latency
let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
- let CompleteModel = 0;
+ let CompleteModel = false;
// TODO: supported, but haven't added scheduling info yet.
let UnsupportedFeatures = [HasStdExtZbkb, HasStdExtZbkc, HasStdExtZbkx,
HasStdExtZcmt, HasStdExtZknd, HasStdExtZkne,
HasStdExtZknh, HasStdExtZksed, HasStdExtZksh,
- HasStdExtZkr, HasVInstructions, HasVInstructionsI64];
+ HasStdExtZkr];
}
let SchedModel = TTAscalonD8Model in {
@@ -34,11 +100,17 @@ let BufferSize = 16 in {
def AscalonFXB : ProcResource<1>; // ALU, INT -> FP/VEC
def AscalonFXC : ProcResource<2>; // ALU, BR
def AscalonFXD : ProcResource<2>; // ALU
- def AscalonFP : ProcResource<2>;
- // TODO: two vector units with vector scheduling model.
+ def AscalonFX : ProcResGroup<[AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXD]>;
+ // FP
+ def AscalonFPA : ProcResource<1>; // Pipe A aslo handles FP/VEC -> INT
+ def AscalonFPB : ProcResource<1>;
+ def AscalonFP : ProcResGroup<[AscalonFPA, AscalonFPB]>;
+ // Vector
+ def AscalonVA : ProcResource<1>;
+ def AscalonVB : ProcResource<1>;
+ def AscalonV : ProcResGroup<[AscalonFPA, AscalonFPB]>;
}
-def AscalonFX : ProcResGroup<[AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXD]>;
//===----------------------------------------------------------------------===//
@@ -316,10 +388,244 @@ def : ReadAdvance<ReadSHXADD32, 0>;
def : ReadAdvance<ReadSingleBit, 0>;
def : ReadAdvance<ReadSingleBitImm, 0>;
+//===----------------------------------------------------------------------===//
+// Vector
+
+// Configuration-Setting Instructions
+let Latency = 1 in {
+def : WriteRes<WriteVSETVLI, [AscalonV]>;
+def : WriteRes<WriteVSETIVLI, [AscalonV]>;
+}
+let Latency = 2 in {
+def : WriteRes<WriteVSETVL, [AscalonV]>;
+}
+
+// Vector Integer Arithmetic Instructions
+foreach mx = SchedMxList in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVIALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICALUMI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVShiftI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMinMaxX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulAddV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMulAddX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMergeI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIMovI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVICmpI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ }
+}
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Widening
+foreach mx = SchedMxListW in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVIWALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIWMulAddX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ }
+}
+// Narrowing
+foreach mx = SchedMxListW in {
+ defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVNShiftV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNShiftI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ }
+}
+
+// Vector Floating-Point Instructions
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ }
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ }
+ }
+}
+foreach mx = SchedMxList in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;
+ }
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVFClassV", [AscalonFP, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMergeV", [AscalonFP, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFMovV", [AscalonFP, AscalonV], mx, IsWorstCase>;
+ }
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVFCmpV", [AscalonFP, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFCmpF", [AscalonFP, AscalonV], mx, IsWorstCase>;
+ }
+}
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
+ defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Widening
+foreach mx = SchedMxListW in {
+ foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;
+ }
+}
+foreach mx = SchedMxListFW in {
+ foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulAddF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtFToFV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
+ }
+ }
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListFW>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in
+ defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;
+}
+// Narrowing
+foreach mx = SchedMxListW in {
+ defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;
+ }
+}
+foreach mx = SchedMxListFW in {
+ foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
+ defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+// Vector Reduction Instructions
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [AscalonFX, AscalonV],
+ mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [AscalonFX, AscalonV],
+ mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxListWRed in {
+ foreach sew = SchedSEWSet<mx, 0, 1>.val in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
+ let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [AscalonFX, AscalonV],
+ mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListF in {
+ foreach sew = SchedSEWSet<mx, 1>.val in {
+ defvar RedCycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
+ let Latency = RedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, RedCycles] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [AscalonFX, AscalonV],
+ mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [AscalonFX, AscalonV],
+ mx, sew, IsWorstCase>;
+ }
+ defvar OrdRedCycles = AscalonGetCyclesLMUL<mx, 18>.c;
+ let Latency = OrdRedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, OrdRedCycles] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [AscalonFX, AscalonV],
+ mx, sew, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxListFWRed in {
+ foreach sew = SchedSEWSet<mx, 1, 1>.val in {
+ defvar RedCycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
+ let Latency = RedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, RedCycles] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [AscalonFX, AscalonV],
+ mx, sew, IsWorstCase>;
+ defvar OrdRedCycles = AscalonGetCyclesLMUL<mx, 18>.c;
+ let Latency = OrdRedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, OrdRedCycles] in
+ defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [AscalonFX, AscalonV],
+ mx, sew, IsWorstCase>;
+ }
+}
+
//===----------------------------------------------------------------------===//
// Unsupported extensions
defm : UnsupportedSchedQ;
-defm : UnsupportedSchedV;
defm : UnsupportedSchedZabha;
defm : UnsupportedSchedZbc;
defm : UnsupportedSchedZbkb;
>From fce1328e1acdafd59ead13311f30801f5976135b Mon Sep 17 00:00:00 2001
From: Petr Penzin <ppenzin at tenstorrent.com>
Date: Mon, 10 Nov 2025 16:08:36 -0600
Subject: [PATCH 2/9] Simplify release/acquire
Out of order cores don't necessarily need to chain acquire-at and
release-at cycles.
---
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 42 +++++++++----------
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index 973e55b5c53f8..adc8b16474b30 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -404,7 +404,7 @@ def : WriteRes<WriteVSETVL, [AscalonV]>;
foreach mx = SchedMxList in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULWriteResMX<"WriteVIALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -438,7 +438,7 @@ foreach mx = SchedMxList in {
foreach sew = SchedSEWSet<mx>.val in {
defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;
}
@@ -449,7 +449,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxListW in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULWriteResMX<"WriteVIWALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIWALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIWALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -463,7 +463,7 @@ foreach mx = SchedMxListW in {
foreach mx = SchedMxListW in {
defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULWriteResMX<"WriteVNShiftV", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNShiftX", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNShiftI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -475,7 +475,7 @@ foreach mx = SchedMxListF in {
foreach sew = SchedSEWSet<mx, isF=1>.val in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
@@ -484,8 +484,6 @@ foreach mx = SchedMxListF in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulAddF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFRecpV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFCvtIToFV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
- }
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFMinMaxF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFSgnjV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
@@ -496,15 +494,15 @@ foreach mx = SchedMxListF in {
foreach mx = SchedMxList in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;
}
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULWriteResMX<"WriteVFClassV", [AscalonFP, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMergeV", [AscalonFP, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMovV", [AscalonFP, AscalonV], mx, IsWorstCase>;
}
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULWriteResMX<"WriteVFCmpV", [AscalonFP, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFCmpF", [AscalonFP, AscalonV], mx, IsWorstCase>;
}
@@ -513,7 +511,7 @@ foreach mx = SchedMxListF in {
foreach sew = SchedSEWSet<mx, isF=1>.val in {
defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
@@ -526,7 +524,7 @@ foreach mx = SchedMxListW in {
foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;
}
}
@@ -534,7 +532,7 @@ foreach mx = SchedMxListFW in {
foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
@@ -546,14 +544,14 @@ foreach mx = SchedMxListFW in {
}
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListFW>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in
defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;
}
// Narrowing
foreach mx = SchedMxListW in {
defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;
}
}
@@ -561,7 +559,7 @@ foreach mx = SchedMxListFW in {
foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;
}
@@ -573,7 +571,7 @@ foreach mx = SchedMxList in {
foreach sew = SchedSEWSet<mx>.val in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [AscalonFX, AscalonV],
@@ -586,7 +584,7 @@ foreach mx = SchedMxListWRed in {
foreach sew = SchedSEWSet<mx, 0, 1>.val in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
- let Latency = Cycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, Cycles] in
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in
defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
}
@@ -596,14 +594,14 @@ foreach mx = SchedMxListF in {
foreach sew = SchedSEWSet<mx, 1>.val in {
defvar RedCycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
- let Latency = RedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, RedCycles] in {
+ let Latency = RedCycles, ReleaseAtCycles = [1, !sub(RedCycles, 1)] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
}
defvar OrdRedCycles = AscalonGetCyclesLMUL<mx, 18>.c;
- let Latency = OrdRedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, OrdRedCycles] in
+ let Latency = OrdRedCycles, ReleaseAtCycles = [1, !sub(OrdRedCycles, 1)] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
}
@@ -613,11 +611,11 @@ foreach mx = SchedMxListFWRed in {
foreach sew = SchedSEWSet<mx, 1, 1>.val in {
defvar RedCycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
- let Latency = RedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, RedCycles] in
+ let Latency = RedCycles, ReleaseAtCycles = [1, !sub(RedCycles, 1)] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
defvar OrdRedCycles = AscalonGetCyclesLMUL<mx, 18>.c;
- let Latency = OrdRedCycles, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, OrdRedCycles] in
+ let Latency = OrdRedCycles, ReleaseAtCycles = [1, !sub(OrdRedCycles, 1)] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
}
>From 7ef8e9822c3ba92affe34bfccafa3eb6819f71e4 Mon Sep 17 00:00:00 2001
From: Petr Penzin <ppenzin at tenstorrent.com>
Date: Wed, 12 Nov 2025 11:37:02 -0600
Subject: [PATCH 3/9] Add vector mask and permute operations
---
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index adc8b16474b30..dabb5d157fa05 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -621,6 +621,67 @@ foreach mx = SchedMxListFWRed in {
}
}
+// Vector Mask Instructions
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 1 in {
+ defm "" : LMULWriteResMX<"WriteVMALUV", [AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMSFSV", [AscalonV], mx, IsWorstCase>;
+ }
+ let Latency = 2, ReleaseAtCycles = [1, 2] in {
+ defm "" : LMULWriteResMX<"WriteVMPopV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMFFSV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ }
+}
+foreach mx = SchedMxList in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ defm "" : LMULWriteResMX<"WriteVIotaV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVIdxV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ }
+}
+
+// Vector Permutation Instructions
+let Latency = 2, ReleaseAtCycles = [1, 2] in {
+ def : WriteRes<WriteVMovSX, [AscalonFX, AscalonV]>;
+ def : WriteRes<WriteVMovXS, [AscalonFX, AscalonV]>;
+ def : WriteRes<WriteVMovSF, [AscalonFX, AscalonV]>;
+ def : WriteRes<WriteVMovFS, [AscalonFX, AscalonV]>;
+}
+foreach mx = SchedMxList in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !mul(Cycles, 2), ReleaseAtCycles = [Cycles, !mul(Cycles, 2)] in {
+ defm "" : LMULWriteResMX<"WriteVRGatherVX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVRGatherVI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ }
+}
+
+foreach mx = SchedMxList in {
+ foreach sew = SchedSEWSet<mx>.val in {
+ defvar Cycles = AscalonGetCyclesVRGatherVV<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
+ let Latency = !add(Cycles, 3), ReleaseAtCycles = [1, !add(1, Cycles)] in {
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherVV", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVRGatherEI16VV", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;
+ defm "" : LMULSEWWriteResMXSEW<"WriteVCompressV", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;
+ }
+ }
+}
+
+foreach mx = SchedMxList in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
+ defm "" : LMULWriteResMX<"WriteVSlideUpX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideDownX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSlideI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVISlide1X", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVFSlide1F", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ }
+}
+
//===----------------------------------------------------------------------===//
// Unsupported extensions
defm : UnsupportedSchedQ;
>From 4c9407e836d56c2aea721537aa6df68f1ae31088 Mon Sep 17 00:00:00 2001
From: Petr Penzin <ppenzin at tenstorrent.com>
Date: Wed, 12 Nov 2025 13:11:30 -0600
Subject: [PATCH 4/9] Add read advances and a few more instructions
Add as number of read advances, VExtV, and VRGatherVV cost function.
---
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 165 +++++++++++++++++-
1 file changed, 164 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index dabb5d157fa05..08e6332613c69 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -65,13 +65,25 @@ class AscalonGetCyclesNarrowing<string mx> {
class AscalonGetCyclesDivOrSqrt<string mx, int sew> {
int c = !cond(
- !eq(sew, 8) : AscalonGetCyclesLMUL<mx, 7>.c, // TODO not valid for fp
+ !eq(sew, 8) : AscalonGetCyclesLMUL<mx, 7>.c,
!eq(sew, 16) : AscalonGetCyclesLMUL<mx, 6>.c,
!eq(sew, 32) : AscalonGetCyclesLMUL<mx, 5>.c,
!eq(sew, 64) : AscalonGetCyclesLMUL<mx, 8>.c
);
}
+class AscalonGetCyclesVRGatherVV<string mx> {
+ int c = !cond(
+ !eq(mx, "M1") : 2,
+ !eq(mx, "M2") : 4,
+ !eq(mx, "M4") : 12,
+ !eq(mx, "M8") : 48,
+ !eq(mx, "MF2") : 2,
+ !eq(mx, "MF4") : 2,
+ !eq(mx, "MF8") : 2
+ );
+}
+
//===----------------------------------------------------------------------===//
def TTAscalonD8Model : SchedMachineModel {
@@ -434,6 +446,13 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVICmpI", [AscalonFX, AscalonV], mx, IsWorstCase>;
}
}
+foreach mx = SchedMxList in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ defm "" : LMULWriteResMX<"WriteVExtV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ }
+}
foreach mx = SchedMxList in {
foreach sew = SchedSEWSet<mx>.val in {
defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;
@@ -682,6 +701,150 @@ foreach mx = SchedMxList in {
}
}
+// Whole vector register move, vmv<N>.v, LMUL aware
+let Latency = 1, ReleaseAtCycles = [1] in
+ def : WriteRes<WriteVMov1V, [AscalonV]>;
+let Latency = 2, ReleaseAtCycles = [2] in
+ def : WriteRes<WriteVMov2V, [AscalonV]>;
+let Latency = 4, ReleaseAtCycles = [4] in
+ def : WriteRes<WriteVMov4V, [AscalonV]>;
+let Latency = 8, ReleaseAtCycles = [8] in
+ def : WriteRes<WriteVMov8V, [AscalonV]>;
+
+// Vector Integer Arithmetic Instructions
+defm : LMULReadAdvance<"ReadVIALUV", 0>;
+defm : LMULReadAdvance<"ReadVIALUX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWALUX", 0>;
+defm : LMULReadAdvance<"ReadVExtV", 0>;
+defm : LMULReadAdvance<"ReadVICALUV", 0>;
+defm : LMULReadAdvance<"ReadVICALUX", 0>;
+defm : LMULReadAdvance<"ReadVShiftV", 0>;
+defm : LMULReadAdvance<"ReadVShiftX", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftV", 0>;
+defm : LMULReadAdvanceW<"ReadVNShiftX", 0>;
+defm : LMULReadAdvance<"ReadVICmpV", 0>;
+defm : LMULReadAdvance<"ReadVICmpX", 0>;
+defm : LMULReadAdvance<"ReadVIMinMaxV", 0>;
+defm : LMULReadAdvance<"ReadVIMinMaxX", 0>;
+defm : LMULReadAdvance<"ReadVIMulV", 0>;
+defm : LMULReadAdvance<"ReadVIMulX", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivV", 0>;
+defm : LMULSEWReadAdvance<"ReadVIDivX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulX", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddV", 0>;
+defm : LMULReadAdvance<"ReadVIMulAddX", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddV", 0>;
+defm : LMULReadAdvanceW<"ReadVIWMulAddX", 0>;
+defm : LMULReadAdvance<"ReadVIMergeV", 0>;
+defm : LMULReadAdvance<"ReadVIMergeX", 0>;
+defm : LMULReadAdvance<"ReadVIMovV", 0>;
+defm : LMULReadAdvance<"ReadVIMovX", 0>;
+
+// Vector Fixed-Point Arithmetic Instructions
+defm "" : LMULReadAdvance<"ReadVSALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVSALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVAALUX", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulV", 0>;
+defm "" : LMULReadAdvance<"ReadVSMulX", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftV", 0>;
+defm "" : LMULReadAdvance<"ReadVSShiftX", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVNClipX", 0>;
+
+// Vector Floating-Point Instructions
+defm "" : LMULSEWReadAdvanceF<"ReadVFALUV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFALUF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWALUF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFDivF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWMulAddF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSqrtV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFRecpV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFMinMaxF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjV", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFSgnjF", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCmpF", 0>;
+defm "" : LMULReadAdvance<"ReadVFClassV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeV", 0>;
+defm "" : LMULReadAdvance<"ReadVFMergeF", 0>;
+defm "" : LMULReadAdvance<"ReadVFMovF", 0>;
+defm "" : LMULSEWReadAdvanceF<"ReadVFCvtIToFV", 0>;
+defm "" : LMULReadAdvance<"ReadVFCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceW<"ReadVFWCvtIToFV", 0>;
+defm "" : LMULReadAdvanceFW<"ReadVFWCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFWCvtFToFV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtIToFV", 0>;
+defm "" : LMULReadAdvanceW<"ReadVFNCvtFToIV", 0>;
+defm "" : LMULSEWReadAdvanceFW<"ReadVFNCvtFToFV", 0>;
+
+// Vector Reduction Instructions
+def : ReadAdvance<ReadVIRedV, 0>;
+def : ReadAdvance<ReadVIRedV0, 0>;
+def : ReadAdvance<ReadVIWRedV, 0>;
+def : ReadAdvance<ReadVIWRedV0, 0>;
+def : ReadAdvance<ReadVFRedV, 0>;
+def : ReadAdvance<ReadVFRedV0, 0>;
+def : ReadAdvance<ReadVFRedOV, 0>;
+def : ReadAdvance<ReadVFRedOV0, 0>;
+def : ReadAdvance<ReadVFWRedV, 0>;
+def : ReadAdvance<ReadVFWRedV0, 0>;
+def : ReadAdvance<ReadVFWRedOV, 0>;
+def : ReadAdvance<ReadVFWRedOV0, 0>;
+
+// Vector Mask Instructions
+defm "" : LMULReadAdvance<"ReadVMALUV", 0>;
+defm "" : LMULReadAdvance<"ReadVMPopV", 0>;
+defm "" : LMULReadAdvance<"ReadVMFFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVMSFSV", 0>;
+defm "" : LMULReadAdvance<"ReadVIotaV", 0>;
+
+// Vector Permutation Instructions
+def : ReadAdvance<ReadVMovXS, 0>;
+def : ReadAdvance<ReadVMovSX_V, 0>;
+def : ReadAdvance<ReadVMovSX_X, 0>;
+def : ReadAdvance<ReadVMovFS, 0>;
+def : ReadAdvance<ReadVMovSF_V, 0>;
+def : ReadAdvance<ReadVMovSF_F, 0>;
+defm "" : LMULReadAdvance<"ReadVISlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVISlideX", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideV", 0>;
+defm "" : LMULReadAdvance<"ReadVFSlideF", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherVV_index", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVRGatherEI16VV_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_data", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVX_index", 0>;
+defm "" : LMULReadAdvance<"ReadVRGatherVI_data", 0>;
+defm "" : LMULSEWReadAdvance<"ReadVCompressV", 0>;
+// LMUL Aware
+def : ReadAdvance<ReadVMov1V, 0>;
+def : ReadAdvance<ReadVMov2V, 0>;
+def : ReadAdvance<ReadVMov4V, 0>;
+def : ReadAdvance<ReadVMov8V, 0>;
+
+// Others
+def : ReadAdvance<ReadVMask, 0>;
+def : ReadAdvance<ReadVPassthru_WorstCase, 0>;
+foreach mx = SchedMxList in {
+ def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx), 0>;
+ foreach sew = SchedSEWSet<mx>.val in
+ def : ReadAdvance<!cast<SchedRead>("ReadVPassthru_" # mx # "_E" # sew), 0>;
+}
+
//===----------------------------------------------------------------------===//
// Unsupported extensions
defm : UnsupportedSchedQ;
>From 2f570d64c27845028e335d8f1c14209c05754e37 Mon Sep 17 00:00:00 2001
From: Petr Penzin <ppenzin at tenstorrent.com>
Date: Wed, 12 Nov 2025 17:19:29 -0600
Subject: [PATCH 5/9] Vector memory ops
---
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 207 ++++++++++++++++++
1 file changed, 207 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index 08e6332613c69..614e8255df9bf 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -84,6 +84,15 @@ class AscalonGetCyclesVRGatherVV<string mx> {
);
}
+class AscalonGetCyclesStridedSegmented<string mx, int sew> {
+ int c = !cond(
+ !eq(sew, 8) : AscalonGetCyclesLMULFractional<mx, 4>.c,
+ !eq(sew, 16) : AscalonGetCyclesLMULFractional<mx, 2>.c,
+ !eq(sew, 32) : AscalonGetCyclesLMULFractional<mx, 1>.c,
+ !eq(sew, 64) : AscalonGetCyclesLMULFractional<mx, 1>.c
+ );
+}
+
//===----------------------------------------------------------------------===//
def TTAscalonD8Model : SchedMachineModel {
@@ -402,6 +411,7 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
//===----------------------------------------------------------------------===//
// Vector
+def : WriteRes<WriteRdVLENB, [AscalonFXA]>;
// Configuration-Setting Instructions
let Latency = 1 in {
@@ -412,6 +422,203 @@ let Latency = 2 in {
def : WriteRes<WriteVSETVL, [AscalonV]>;
}
+// Vector Loads and Stores
+foreach mx = SchedMxList in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
+ defm "" : LMULWriteResMX<"WriteVLDE", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDFF", [AscalonLS], mx, IsWorstCase>;
+ }
+ let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in
+ defm "" : LMULWriteResMX<"WriteVSTE", [AscalonLS], mx, IsWorstCase>;
+}
+
+foreach mx = SchedMxList in {
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 1, ReleaseAtCycles = [1] in
+ defm "" : LMULWriteResMX<"WriteVLDM", [AscalonLS], mx, IsWorstCase>;
+ let Latency = 1, ReleaseAtCycles = [1] in
+ defm "" : LMULWriteResMX<"WriteVSTM", [AscalonLS], mx, IsWorstCase>;
+}
+
+foreach mx = SchedMxList in {
+ defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(3, Cycles), AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ defm "" : LMULWriteResMX<"WriteVLDS8", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX8", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX8", [AscalonLS], mx, IsWorstCase>;
+ }
+ let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ defm "" : LMULWriteResMX<"WriteVSTS8", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX8", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX8", [AscalonLS], mx, IsWorstCase>;
+ }
+}
+foreach mx = ["MF4", "MF2", "M1", "M2", "M4", "M8"] in {
+ defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(3, Cycles), AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ defm "" : LMULWriteResMX<"WriteVLDS16", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX16", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX16", [AscalonLS], mx, IsWorstCase>;
+ }
+ let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ defm "" : LMULWriteResMX<"WriteVSTS16", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX16", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX16", [AscalonLS], mx, IsWorstCase>;
+ }
+}
+foreach mx = ["MF2", "M1", "M2", "M4", "M8"] in {
+ defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(3, Cycles), AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ defm "" : LMULWriteResMX<"WriteVLDS32", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX32", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX32", [AscalonLS], mx, IsWorstCase>;
+ }
+ let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ defm "" : LMULWriteResMX<"WriteVSTS32", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX32", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX32", [AscalonLS], mx, IsWorstCase>;
+ }
+}
+foreach mx = ["M1", "M2", "M4", "M8"] in {
+ defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = !add(3, Cycles), AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ defm "" : LMULWriteResMX<"WriteVLDS64", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDUX64", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLDOX64", [AscalonLS], mx, IsWorstCase>;
+ }
+ let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ defm "" : LMULWriteResMX<"WriteVSTS64", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTUX64", [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSTOX64", [AscalonLS], mx, IsWorstCase>;
+ }
+}
+
+let Latency = 1 in {
+ // VLD*R is LMUL aware
+ def : WriteRes<WriteVLD1R, [AscalonLS]>;
+ def : WriteRes<WriteVLD2R, [AscalonLS]>;
+ def : WriteRes<WriteVLD4R, [AscalonLS]>;
+ def : WriteRes<WriteVLD8R, [AscalonLS]>;
+ // VST*R is LMUL aware
+ def : WriteRes<WriteVST1R, [AscalonLS]>;
+ def : WriteRes<WriteVST2R, [AscalonLS]>;
+ def : WriteRes<WriteVST4R, [AscalonLS]>;
+ def : WriteRes<WriteVST8R, [AscalonLS]>;
+}
+
+// Segmented Loads and Stores
+foreach mx = SchedMxList in {
+ foreach eew = [8, 16, 32, 64] in {
+ foreach nf=2-8 in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ // Does not chain so set latency high
+ let Latency = !add(3, Cycles), AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
+ }
+ let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in
+ defm "" : LMULWriteResMX<"WriteVSSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
+ }
+ }
+}
+foreach mx = SchedMxList in {
+ foreach nf=2-8 in {
+ foreach eew = [8, 16, 32, 64] in {
+ defvar Cycles = AscalonGetCyclesStridedSegmented<mx, eew>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ // Does not chain so set latency high
+ let Latency = !add(3, Cycles), AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
+ }
+ let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
+ }
+ }
+ }
+}
+
+// Vector Fixed-Point Arithmetic Instructions
+foreach mx = SchedMxList in {
+ defvar Cycles = AscalonGetCyclesDefault<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
+ let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
+ // FIXME what pipe does this occupy aside from vec
+ defm "" : LMULWriteResMX<"WriteVSALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVAALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSMulV", [AscalonFXA, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSMulX", [AscalonFXA, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftV", [AscalonFX, AscalonV], mx, IsWorstCase>; // TODO correct?
+ defm "" : LMULWriteResMX<"WriteVSShiftX", [AscalonFX, AscalonV], mx, IsWorstCase>; // TODO correct?
+ defm "" : LMULWriteResMX<"WriteVSShiftI", [AscalonFX, AscalonV], mx, IsWorstCase>; // TODO correct?
+ }
+}
+// Narrowing
+foreach mx = SchedMxListW in {
+ defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
+ defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
+ let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
+ // TODO verify
+ defm "" : LMULWriteResMX<"WriteVNClipV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVNClipI", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ }
+}
+
+// Configuration-Setting Instructions
+def : ReadAdvance<ReadVSETVLI, 1>;
+def : ReadAdvance<ReadVSETVL, 1>;
+
+// Vector Loads and Stores
+def : ReadAdvance<ReadVLDX, 0>;
+def : ReadAdvance<ReadVSTX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTEV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTM", 0>;
+def : ReadAdvance<ReadVLDSX, 0>;
+def : ReadAdvance<ReadVSTSX, 0>;
+defm "" : LMULReadAdvance<"ReadVSTS8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTS64V", 0>;
+defm "" : LMULReadAdvance<"ReadVLDUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVLDOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTUX64V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOXV", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX8V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX16V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX32V", 0>;
+defm "" : LMULReadAdvance<"ReadVSTOX64V", 0>;
+// LMUL Aware
+def : ReadAdvance<ReadVST1R, 0>;
+def : ReadAdvance<ReadVST2R, 0>;
+def : ReadAdvance<ReadVST4R, 0>;
+def : ReadAdvance<ReadVST8R, 0>;
+
// Vector Integer Arithmetic Instructions
foreach mx = SchedMxList in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
>From da7d9bb8dda7c4ff3aa41ddfccaa4085e2caab57 Mon Sep 17 00:00:00 2001
From: Petr Penzin <ppenzin at tenstorrent.com>
Date: Wed, 12 Nov 2025 16:45:10 -0800
Subject: [PATCH 6/9] Update llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
Co-authored-by: Craig Topper <craig.topper at sifive.com>
---
llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index 614e8255df9bf..de6c1f59195fa 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -123,7 +123,7 @@ let BufferSize = 16 in {
def AscalonFXD : ProcResource<2>; // ALU
def AscalonFX : ProcResGroup<[AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXD]>;
// FP
- def AscalonFPA : ProcResource<1>; // Pipe A aslo handles FP/VEC -> INT
+ def AscalonFPA : ProcResource<1>; // Pipe A also handles FP/VEC -> INT
def AscalonFPB : ProcResource<1>;
def AscalonFP : ProcResGroup<[AscalonFPA, AscalonFPB]>;
// Vector
>From 2179e4c7a6f88954aee16c5562e189d232381727 Mon Sep 17 00:00:00 2001
From: Petr Penzin <ppenzin at tenstorrent.com>
Date: Wed, 12 Nov 2025 18:55:16 -0600
Subject: [PATCH 7/9] Clean up copied latencies, remove TODOs
---
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 40 ++++++-------------
1 file changed, 13 insertions(+), 27 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index de6c1f59195fa..67e07542f112c 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -426,31 +426,29 @@ def : WriteRes<WriteVSETVL, [AscalonV]>;
foreach mx = SchedMxList in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
+ let Latency = Cycles in {
defm "" : LMULWriteResMX<"WriteVLDE", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDFF", [AscalonLS], mx, IsWorstCase>;
}
- let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in
+ let Latency = 1 in
defm "" : LMULWriteResMX<"WriteVSTE", [AscalonLS], mx, IsWorstCase>;
}
foreach mx = SchedMxList in {
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 1, ReleaseAtCycles = [1] in
+ let Latency = 1 in
defm "" : LMULWriteResMX<"WriteVLDM", [AscalonLS], mx, IsWorstCase>;
- let Latency = 1, ReleaseAtCycles = [1] in
+ let Latency = 1 in
defm "" : LMULWriteResMX<"WriteVSTM", [AscalonLS], mx, IsWorstCase>;
}
foreach mx = SchedMxList in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = !add(3, Cycles), AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ let Latency = Cycles in {
defm "" : LMULWriteResMX<"WriteVLDS8", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX8", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX8", [AscalonLS], mx, IsWorstCase>;
- }
- let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
defm "" : LMULWriteResMX<"WriteVSTS8", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTUX8", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTOX8", [AscalonLS], mx, IsWorstCase>;
@@ -459,12 +457,10 @@ foreach mx = SchedMxList in {
foreach mx = ["MF4", "MF2", "M1", "M2", "M4", "M8"] in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = !add(3, Cycles), AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ let Latency = Cycles in {
defm "" : LMULWriteResMX<"WriteVLDS16", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX16", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX16", [AscalonLS], mx, IsWorstCase>;
- }
- let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
defm "" : LMULWriteResMX<"WriteVSTS16", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTUX16", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTOX16", [AscalonLS], mx, IsWorstCase>;
@@ -473,12 +469,10 @@ foreach mx = ["MF4", "MF2", "M1", "M2", "M4", "M8"] in {
foreach mx = ["MF2", "M1", "M2", "M4", "M8"] in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = !add(3, Cycles), AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ let Latency = Cycles in {
defm "" : LMULWriteResMX<"WriteVLDS32", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX32", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX32", [AscalonLS], mx, IsWorstCase>;
- }
- let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
defm "" : LMULWriteResMX<"WriteVSTS32", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTUX32", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTOX32", [AscalonLS], mx, IsWorstCase>;
@@ -487,12 +481,10 @@ foreach mx = ["MF2", "M1", "M2", "M4", "M8"] in {
foreach mx = ["M1", "M2", "M4", "M8"] in {
defvar Cycles = AscalonGetCyclesLMUL<mx, 2>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = !add(3, Cycles), AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ let Latency = Cycles in {
defm "" : LMULWriteResMX<"WriteVLDS64", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDUX64", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDOX64", [AscalonLS], mx, IsWorstCase>;
- }
- let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
defm "" : LMULWriteResMX<"WriteVSTS64", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTUX64", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSTOX64", [AscalonLS], mx, IsWorstCase>;
@@ -518,8 +510,7 @@ foreach mx = SchedMxList in {
foreach nf=2-8 in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- // Does not chain so set latency high
- let Latency = !add(3, Cycles), AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ let Latency = Cycles in {
defm "" : LMULWriteResMX<"WriteVLSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLSEGFF" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
}
@@ -533,13 +524,10 @@ foreach mx = SchedMxList in {
foreach eew = [8, 16, 32, 64] in {
defvar Cycles = AscalonGetCyclesStridedSegmented<mx, eew>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- // Does not chain so set latency high
- let Latency = !add(3, Cycles), AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
+ let Latency = Cycles in {
defm "" : LMULWriteResMX<"WriteVLSSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLUXSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLOXSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
- }
- let Latency = 1, AcquireAtCycles = [1], ReleaseAtCycles = [!add(1, Cycles)] in {
defm "" : LMULWriteResMX<"WriteVSSSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSUXSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSOXSEG" # nf # "e" # eew, [AscalonLS], mx, IsWorstCase>;
@@ -553,7 +541,6 @@ foreach mx = SchedMxList in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
- // FIXME what pipe does this occupy aside from vec
defm "" : LMULWriteResMX<"WriteVSALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -561,9 +548,9 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVAALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSMulV", [AscalonFXA, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSMulX", [AscalonFXA, AscalonV], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVSShiftV", [AscalonFX, AscalonV], mx, IsWorstCase>; // TODO correct?
- defm "" : LMULWriteResMX<"WriteVSShiftX", [AscalonFX, AscalonV], mx, IsWorstCase>; // TODO correct?
- defm "" : LMULWriteResMX<"WriteVSShiftI", [AscalonFX, AscalonV], mx, IsWorstCase>; // TODO correct?
+ defm "" : LMULWriteResMX<"WriteVSShiftV", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftX", [AscalonFX, AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVSShiftI", [AscalonFX, AscalonV], mx, IsWorstCase>;
}
}
// Narrowing
@@ -571,7 +558,6 @@ foreach mx = SchedMxListW in {
defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
- // TODO verify
defm "" : LMULWriteResMX<"WriteVNClipV", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNClipX", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNClipI", [AscalonFX, AscalonV], mx, IsWorstCase>;
>From 88279d3ff7ee2e4d6bb35c76c2bb3d24eb9b3c1a Mon Sep 17 00:00:00 2001
From: Petr Penzin <ppenzin at tenstorrent.com>
Date: Thu, 13 Nov 2025 16:42:05 -0600
Subject: [PATCH 8/9] Clear instances of cycles-1=0, add tests
---
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 50 +-
.../tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s | 54 +-
.../tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s | 54 +-
.../llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s | 1009 ++++
.../llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s | 107 +
.../RISCV/tt-ascalon-d8/vle-vse-vlm.s | 542 ++
.../llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s | 316 ++
.../RISCV/tt-ascalon-d8/vlseg-vsseg.s | 4727 +++++++++++++++++
.../llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s | 588 ++
.../tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s | 893 ++++
.../llvm-mca/RISCV/tt-ascalon-d8/vreduce.s | 436 ++
.../RISCV/tt-ascalon-d8/vrgather-vcompress.s | 84 +
.../RISCV/tt-ascalon-d8/vshift-vmul.s | 130 +
13 files changed, 8911 insertions(+), 79 deletions(-)
create mode 100644 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
create mode 100644 llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index 67e07542f112c..cc5b75621fa2e 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -129,7 +129,7 @@ let BufferSize = 16 in {
// Vector
def AscalonVA : ProcResource<1>;
def AscalonVB : ProcResource<1>;
- def AscalonV : ProcResGroup<[AscalonFPA, AscalonFPB]>;
+ def AscalonV : ProcResGroup<[AscalonVA, AscalonVB]>;
}
@@ -540,7 +540,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULWriteResMX<"WriteVSALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVSALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -557,7 +557,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxListW in {
defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = 8, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULWriteResMX<"WriteVNClipV", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNClipX", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNClipI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -609,7 +609,7 @@ def : ReadAdvance<ReadVST8R, 0>;
foreach mx = SchedMxList in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULWriteResMX<"WriteVIALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -642,7 +642,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULWriteResMX<"WriteVExtV", [AscalonFX, AscalonV], mx, IsWorstCase>;
}
}
@@ -650,7 +650,7 @@ foreach mx = SchedMxList in {
foreach sew = SchedSEWSet<mx>.val in {
defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVIDivV", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVIDivX", [AscalonFX, AscalonV], mx, sew, IsWorstCase>;
}
@@ -661,7 +661,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxListW in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULWriteResMX<"WriteVIWALUV", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIWALUX", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIWALUI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -675,7 +675,7 @@ foreach mx = SchedMxListW in {
foreach mx = SchedMxListW in {
defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULWriteResMX<"WriteVNShiftV", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNShiftX", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVNShiftI", [AscalonFX, AscalonV], mx, IsWorstCase>;
@@ -687,7 +687,7 @@ foreach mx = SchedMxListF in {
foreach sew = SchedSEWSet<mx, isF=1>.val in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, isF=1>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFALUF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFMulV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
@@ -706,15 +706,11 @@ foreach mx = SchedMxListF in {
foreach mx = SchedMxList in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULWriteResMX<"WriteVFCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;
- }
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULWriteResMX<"WriteVFClassV", [AscalonFP, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMergeV", [AscalonFP, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFMovV", [AscalonFP, AscalonV], mx, IsWorstCase>;
- }
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
defm "" : LMULWriteResMX<"WriteVFCmpV", [AscalonFP, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVFCmpF", [AscalonFP, AscalonV], mx, IsWorstCase>;
}
@@ -723,7 +719,7 @@ foreach mx = SchedMxListF in {
foreach sew = SchedSEWSet<mx, isF=1>.val in {
defvar Cycles = AscalonGetCyclesDivOrSqrt<mx, sew>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFSqrtV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFDivV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFDivF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
@@ -736,7 +732,7 @@ foreach mx = SchedMxListW in {
foreach sew = SchedSEWSet<mx, isF=0, isWidening=1>.val in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListW>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFWCvtIToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;
}
}
@@ -744,7 +740,7 @@ foreach mx = SchedMxListFW in {
foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFWALUF", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFWMulV", [AscalonFP, AscalonV], mx, sew, IsWorstCase>;
@@ -756,14 +752,14 @@ foreach mx = SchedMxListFW in {
}
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListFW>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in
defm "" : LMULWriteResMX<"WriteVFWCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;
}
// Narrowing
foreach mx = SchedMxListW in {
defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxListW>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULWriteResMX<"WriteVFNCvtFToIV", [AscalonFPA, AscalonV], mx, IsWorstCase>;
}
}
@@ -771,7 +767,7 @@ foreach mx = SchedMxListFW in {
foreach sew = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
defvar Cycles = AscalonGetCyclesNarrowing<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFW, isF=1>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtIToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFNCvtFToFV", [AscalonFXB, AscalonV], mx, sew, IsWorstCase>;
}
@@ -783,7 +779,7 @@ foreach mx = SchedMxList in {
foreach sew = SchedSEWSet<mx>.val in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [AscalonFX, AscalonV],
@@ -796,7 +792,7 @@ foreach mx = SchedMxListWRed in {
foreach sew = SchedSEWSet<mx, 0, 1>.val in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListWRed>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVIWRedV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
}
@@ -806,14 +802,14 @@ foreach mx = SchedMxListF in {
foreach sew = SchedSEWSet<mx, 1>.val in {
defvar RedCycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
- let Latency = RedCycles, ReleaseAtCycles = [1, !sub(RedCycles, 1)] in {
+ let Latency = RedCycles, ReleaseAtCycles = [1, RedCycles] in {
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedMinMaxV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
}
defvar OrdRedCycles = AscalonGetCyclesLMUL<mx, 18>.c;
- let Latency = OrdRedCycles, ReleaseAtCycles = [1, !sub(OrdRedCycles, 1)] in
+ let Latency = OrdRedCycles, ReleaseAtCycles = [1, OrdRedCycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFRedOV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
}
@@ -823,11 +819,11 @@ foreach mx = SchedMxListFWRed in {
foreach sew = SchedSEWSet<mx, 1, 1>.val in {
defvar RedCycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMXSEW<mx, sew, SchedMxListFWRed, 1>.c;
- let Latency = RedCycles, ReleaseAtCycles = [1, !sub(RedCycles, 1)] in
+ let Latency = RedCycles, ReleaseAtCycles = [1, RedCycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
defvar OrdRedCycles = AscalonGetCyclesLMUL<mx, 18>.c;
- let Latency = OrdRedCycles, ReleaseAtCycles = [1, !sub(OrdRedCycles, 1)] in
+ let Latency = OrdRedCycles, ReleaseAtCycles = [1, OrdRedCycles] in
defm "" : LMULSEWWriteResMXSEW<"WriteVFWRedOV_From", [AscalonFX, AscalonV],
mx, sew, IsWorstCase>;
}
@@ -848,7 +844,7 @@ foreach mx = SchedMxList in {
foreach mx = SchedMxList in {
defvar Cycles = AscalonGetCyclesDefault<mx>.c;
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = Cycles, ReleaseAtCycles = [1, !sub(Cycles, 1)] in {
+ let Latency = Cycles, ReleaseAtCycles = [1, Cycles] in {
defm "" : LMULWriteResMX<"WriteVIotaV", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVIdxV", [AscalonFX, AscalonV], mx, IsWorstCase>;
}
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s
index 9fd16e1ffc1d6..7f44bd0eccdcb 100644
--- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fp.s
@@ -47,33 +47,35 @@ fsqrt.d ft2, fa3
# CHECK-NEXT: 1 12 6.00 fsqrt.d ft2, fa3
# CHECK: Resources:
-# CHECK-NEXT: [0.0] - AscalonFP
-# CHECK-NEXT: [0.1] - AscalonFP
-# CHECK-NEXT: [1] - AscalonFXA
-# CHECK-NEXT: [2] - AscalonFXB
-# CHECK-NEXT: [3.0] - AscalonFXC
-# CHECK-NEXT: [3.1] - AscalonFXC
-# CHECK-NEXT: [4.0] - AscalonFXD
-# CHECK-NEXT: [4.1] - AscalonFXD
-# CHECK-NEXT: [5.0] - AscalonLS
-# CHECK-NEXT: [5.1] - AscalonLS
-# CHECK-NEXT: [5.2] - AscalonLS
+# CHECK-NEXT: [0] - AscalonFPA
+# CHECK-NEXT: [1] - AscalonFPB
+# CHECK-NEXT: [2] - AscalonFXA
+# CHECK-NEXT: [3] - AscalonFXB
+# CHECK-NEXT: [4.0] - AscalonFXC
+# CHECK-NEXT: [4.1] - AscalonFXC
+# CHECK-NEXT: [5.0] - AscalonFXD
+# CHECK-NEXT: [5.1] - AscalonFXD
+# CHECK-NEXT: [6.0] - AscalonLS
+# CHECK-NEXT: [6.1] - AscalonLS
+# CHECK-NEXT: [6.2] - AscalonLS
+# CHECK-NEXT: [7] - AscalonVA
+# CHECK-NEXT: [8] - AscalonVB
# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2]
-# CHECK-NEXT: 18.00 28.00 - - - - - - - - -
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
+# CHECK-NEXT: 18.00 28.00 - - - - - - - - - - -
# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] Instructions:
-# CHECK-NEXT: - 1.00 - - - - - - - - - fmin.s ft0, fa0, fa1
-# CHECK-NEXT: 1.00 - - - - - - - - - - fmax.s ft1, fa0, fa1
-# CHECK-NEXT: - 1.00 - - - - - - - - - fmin.d ft2, ft4, ft5
-# CHECK-NEXT: 1.00 - - - - - - - - - - fmax.d ft3, ft4, ft5
-# CHECK-NEXT: - 1.00 - - - - - - - - - fmadd.s fs0, fs0, fs8, fs9
-# CHECK-NEXT: 1.00 - - - - - - - - - - fmsub.s fs1, fs1, fs8, fs9
-# CHECK-NEXT: - 1.00 - - - - - - - - - fmul.s fs3, fs3, fs4
-# CHECK-NEXT: 7.00 - - - - - - - - - - fdiv.s fs2, fs3, fs4
-# CHECK-NEXT: 1.00 - - - - - - - - - - fmul.d ft4, ft4, ft5
-# CHECK-NEXT: - 12.00 - - - - - - - - - fdiv.d fs4, fa3, ft5
-# CHECK-NEXT: 7.00 - - - - - - - - - - fsqrt.s ft1, fa2
-# CHECK-NEXT: - 12.00 - - - - - - - - - fsqrt.d ft2, fa3
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmin.s ft0, fa0, fa1
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmax.s ft1, fa0, fa1
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmin.d ft2, ft4, ft5
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmax.d ft3, ft4, ft5
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmadd.s fs0, fs0, fs8, fs9
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmsub.s fs1, fs1, fs8, fs9
+# CHECK-NEXT: - 1.00 - - - - - - - - - - - fmul.s fs3, fs3, fs4
+# CHECK-NEXT: 7.00 - - - - - - - - - - - - fdiv.s fs2, fs3, fs4
+# CHECK-NEXT: 1.00 - - - - - - - - - - - - fmul.d ft4, ft4, ft5
+# CHECK-NEXT: - 12.00 - - - - - - - - - - - fdiv.d fs4, fa3, ft5
+# CHECK-NEXT: 7.00 - - - - - - - - - - - - fsqrt.s ft1, fa2
+# CHECK-NEXT: - 12.00 - - - - - - - - - - - fsqrt.d ft2, fa3
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s
index 46cb4c6b8ae24..d10cc3f57e970 100644
--- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/fx.s
@@ -47,33 +47,35 @@ fcvt.w.s t5, f3
# CHECK-NEXT: 1 1 1.00 fcvt.w.s t5, ft3
# CHECK: Resources:
-# CHECK-NEXT: [0.0] - AscalonFP
-# CHECK-NEXT: [0.1] - AscalonFP
-# CHECK-NEXT: [1] - AscalonFXA
-# CHECK-NEXT: [2] - AscalonFXB
-# CHECK-NEXT: [3.0] - AscalonFXC
-# CHECK-NEXT: [3.1] - AscalonFXC
-# CHECK-NEXT: [4.0] - AscalonFXD
-# CHECK-NEXT: [4.1] - AscalonFXD
-# CHECK-NEXT: [5.0] - AscalonLS
-# CHECK-NEXT: [5.1] - AscalonLS
-# CHECK-NEXT: [5.2] - AscalonLS
+# CHECK-NEXT: [0] - AscalonFPA
+# CHECK-NEXT: [1] - AscalonFPB
+# CHECK-NEXT: [2] - AscalonFXA
+# CHECK-NEXT: [3] - AscalonFXB
+# CHECK-NEXT: [4.0] - AscalonFXC
+# CHECK-NEXT: [4.1] - AscalonFXC
+# CHECK-NEXT: [5.0] - AscalonFXD
+# CHECK-NEXT: [5.1] - AscalonFXD
+# CHECK-NEXT: [6.0] - AscalonLS
+# CHECK-NEXT: [6.1] - AscalonLS
+# CHECK-NEXT: [6.2] - AscalonLS
+# CHECK-NEXT: [7] - AscalonVA
+# CHECK-NEXT: [8] - AscalonVB
# CHECK: Resource pressure per iteration:
-# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2]
-# CHECK-NEXT: - - 17.00 1.00 2.00 2.00 1.00 1.00 - - -
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
+# CHECK-NEXT: - - 17.00 1.00 2.00 2.00 1.00 1.00 - - - - -
# CHECK: Resource pressure by instruction:
-# CHECK-NEXT: [0.0] [0.1] [1] [2] [3.0] [3.1] [4.0] [4.1] [5.0] [5.1] [5.2] Instructions:
-# CHECK-NEXT: - - 1.00 - - - - - - - - mul t0, a0, t0
-# CHECK-NEXT: - - - - - - - 1.00 - - - sub s2, a2, a3
-# CHECK-NEXT: - - 7.00 - - - - - - - - div t1, t2, t3
-# CHECK-NEXT: - - - - - - 1.00 - - - - add t1, a4, gp
-# CHECK-NEXT: - - 7.00 - - - - - - - - div a1, a2, a3
-# CHECK-NEXT: - - - - - 1.00 - - - - - add t1, a0, t0
-# CHECK-NEXT: - - 1.00 - - - - - - - - mul s0, s0, a5
-# CHECK-NEXT: - - - - - 1.00 - - - - - add t2, t2, t2
-# CHECK-NEXT: - - - - 1.00 - - - - - - sub s1, s0, s1
-# CHECK-NEXT: - - - 1.00 - - - - - - - fcvt.s.w ft1, t3
-# CHECK-NEXT: - - - - 1.00 - - - - - - add s2, s2, s2
-# CHECK-NEXT: - - 1.00 - - - - - - - - fcvt.w.s t5, ft3
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - mul t0, a0, t0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - - sub s2, a2, a3
+# CHECK-NEXT: - - 7.00 - - - - - - - - - - div t1, t2, t3
+# CHECK-NEXT: - - - - - - 1.00 - - - - - - add t1, a4, gp
+# CHECK-NEXT: - - 7.00 - - - - - - - - - - div a1, a2, a3
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - add t1, a0, t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - mul s0, s0, a5
+# CHECK-NEXT: - - - - - 1.00 - - - - - - - add t2, t2, t2
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - sub s1, s0, s1
+# CHECK-NEXT: - - - 1.00 - - - - - - - - - fcvt.s.w ft1, t3
+# CHECK-NEXT: - - - - 1.00 - - - - - - - - add s2, s2, s2
+# CHECK-NEXT: - - 1.00 - - - - - - - - - - fcvt.w.s t5, ft3
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
new file mode 100644
index 0000000000000..e970391adb63e
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
@@ -0,0 +1,1009 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, mf4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, mf2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m8, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, mf8, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, mf4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, mf2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m8, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, mf8, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, mf4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, mf2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m8, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, mf8, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, mf4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, mf2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m1, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m2, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m4, tu, mu
+vdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m8, tu, mu
+vdiv.vv v8, v16, v24
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, mf4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, mf2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, m2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, m4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e8, m8, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, mf8, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, mf4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, mf2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, m2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, m4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e16, m8, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, mf8, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, mf4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, mf2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, m2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, m4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e32, m8, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e64, mf8, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e64, mf4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e64, mf2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e64, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e64, m1, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e64, m2, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e64, m4, tu, mu
+vdiv.vx v8, v16, a0
+vsetvli zero, zero, e64, m8, tu, mu
+vdiv.vx v8, v16, a0
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, mf4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, mf2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e8, m8, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, mf8, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, mf4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, mf2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e16, m8, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, mf8, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, mf4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, mf2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e32, m8, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, mf8, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, mf4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, mf2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m1, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m2, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m4, tu, mu
+vfdiv.vv v8, v16, v24
+vsetvli zero, zero, e64, m8, tu, mu
+vfdiv.vv v8, v16, v24
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, mf4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, mf2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, m2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, m4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e8, m8, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, mf8, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, mf4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, mf2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, m2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, m4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e16, m8, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, mf8, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, mf4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, mf2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, m2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, m4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e32, m8, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e64, mf8, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e64, mf4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e64, mf2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e64, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e64, m1, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e64, m2, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e64, m4, tu, mu
+vfdiv.vf v8, v16, fa0
+vsetvli zero, zero, e64, m8, tu, mu
+vfdiv.vf v8, v16, fa0
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, mf8, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, mf8, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, mf4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e64, mf8, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e64, mf4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e64, mf2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vfsqrt.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vfsqrt.v v8, v16
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 320
+# CHECK-NEXT: Total Cycles: 2382
+# CHECK-NEXT: Total uOps: 320
+
+# CHECK: Dispatch Width: 8
+# CHECK-NEXT: uOps Per Cycle: 0.13
+# CHECK-NEXT: IPC: 0.13
+# CHECK-NEXT: Block RThroughput: 2359.5
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 3.50 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 3.50 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 3.50 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 3.50 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 3.50 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 14 7.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 28 14.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 3.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 12.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.50 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 20 10.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 40 20.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 8.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 16.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 64 32.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 3.50 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 3.50 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 3.50 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 3.50 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 3.50 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 14 7.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 28 14.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 3.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 12.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.50 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 20 10.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 40 20.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 8.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 16.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 64 32.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 12.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.50 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 20 10.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 40 20.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 8.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 16.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 64 32.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 12.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.50 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 20 10.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 40 20.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 8.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 16.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 64 32.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 12.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.50 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 20 10.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 40 20.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 8.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 16.00 vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 64 32.00 vfsqrt.v v8, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFPA
+# CHECK-NEXT: [1] - AscalonFPB
+# CHECK-NEXT: [2] - AscalonFXA
+# CHECK-NEXT: [3] - AscalonFXB
+# CHECK-NEXT: [4.0] - AscalonFXC
+# CHECK-NEXT: [4.1] - AscalonFXC
+# CHECK-NEXT: [5.0] - AscalonFXD
+# CHECK-NEXT: [5.1] - AscalonFXD
+# CHECK-NEXT: [6.0] - AscalonLS
+# CHECK-NEXT: [6.1] - AscalonLS
+# CHECK-NEXT: [6.2] - AscalonLS
+# CHECK-NEXT: [7] - AscalonVA
+# CHECK-NEXT: [8] - AscalonVB
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
+# CHECK-NEXT: 48.00 48.00 - - - - 32.00 32.00 - - - 2379.00 2340.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 7.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - 7.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 7.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 7.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 7.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - 14.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 28.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - 56.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 56.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - 6.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 6.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - 6.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 6.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 12.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 24.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 48.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 56.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 56.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 5.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - 5.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 5.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - 10.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 20.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 40.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 56.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 56.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 56.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 8.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 8.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 16.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 32.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - 64.00 - vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 7.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 7.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 7.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 7.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 7.00 - vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 14.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 28.00 - vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 56.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 56.00 - vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 6.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 6.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1.00 - - - - - - - - - - - 5.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - 1.00 - - - - - - - - - - 5.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1.00 - - - - - - - - - - - 10.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - 1.00 - - - - - - - - - - 20.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1.00 - - - - - - - - - - 40.00 - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - 1.00 - - - - - - - - - - 48.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1.00 - - - - - - - - - - 48.00 - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - 1.00 - - - - - - - - - - 48.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1.00 - - - - - - - - - - 8.00 - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - 1.00 - - - - - - - - - 8.00 - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1.00 - - - - - - - - - - 16.00 - vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - 1.00 - - - - - - - - - - 32.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1.00 - - - - - - - - - - 64.00 - vfsqrt.v v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
new file mode 100644
index 0000000000000..8771f91f449db
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
@@ -0,0 +1,107 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e32, m2, tu, mu
+vslidedown.vx v5, v7, x6
+
+vsetvli zero, zero, e32, m4, tu, mu
+vslidedown.vx v5, v7, x6
+
+vsetvli zero, zero, e32, m8, tu, mu
+vslidedown.vx v5, v7, x6
+
+vsetvli zero, zero, e32, m2, tu, mu
+vslideup.vx v5, v7, x6
+
+vsetvli zero, zero, e32, m4, tu, mu
+vslideup.vx v5, v7, x6
+
+vsetvli zero, zero, e32, m8, tu, mu
+vslideup.vx v5, v7, x6
+
+vsetvli zero, zero, e32, m2, tu, mu
+vslideup.vx v5, v7, x6, v0.t
+
+vsetvli zero, zero, e32, m4, tu, mu
+vslideup.vx v5, v7, x6, v0.t
+
+vsetvli zero, zero, e32, m8, tu, mu
+vslideup.vx v5, v7, x6, v0.t
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 18
+# CHECK-NEXT: Total Cycles: 31
+# CHECK-NEXT: Total uOps: 18
+
+# CHECK: Dispatch Width: 8
+# CHECK-NEXT: uOps Per Cycle: 0.58
+# CHECK-NEXT: IPC: 0.58
+# CHECK-NEXT: Block RThroughput: 30.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vslidedown.vx v5, v7, t1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vslidedown.vx v5, v7, t1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 vslidedown.vx v5, v7, t1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vslideup.vx v5, v7, t1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vslideup.vx v5, v7, t1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 vslideup.vx v5, v7, t1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 vslideup.vx v5, v7, t1, v0.t
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFPA
+# CHECK-NEXT: [1] - AscalonFPB
+# CHECK-NEXT: [2] - AscalonFXA
+# CHECK-NEXT: [3] - AscalonFXB
+# CHECK-NEXT: [4.0] - AscalonFXC
+# CHECK-NEXT: [4.1] - AscalonFXC
+# CHECK-NEXT: [5.0] - AscalonFXD
+# CHECK-NEXT: [5.1] - AscalonFXD
+# CHECK-NEXT: [6.0] - AscalonLS
+# CHECK-NEXT: [6.1] - AscalonLS
+# CHECK-NEXT: [6.2] - AscalonLS
+# CHECK-NEXT: [7] - AscalonVA
+# CHECK-NEXT: [8] - AscalonVB
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
+# CHECK-NEXT: - - - - - - 4.00 5.00 - - - 27.00 33.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 3.00 vslidedown.vx v5, v7, t1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - 5.00 - vslidedown.vx v5, v7, t1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 9.00 vslidedown.vx v5, v7, t1
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - 3.00 - vslideup.vx v5, v7, t1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 5.00 - vslideup.vx v5, v7, t1
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 9.00 vslideup.vx v5, v7, t1
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 3.00 - vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - 5.00 - vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 9.00 vslideup.vx v5, v7, t1, v0.t
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
new file mode 100644
index 0000000000000..479aacc1a6e9d
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
@@ -0,0 +1,542 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64.v v8, (a0)
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vse8.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vse8.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vse16.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vse16.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vse32.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vse32.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vse64.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vse64.v v8, (a0)
+
+# Unit-stride mask load/store
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vlm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vlm.v v8, (a0)
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vsm.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vsm.v v8, (a0)
+
+# Fault-only-first
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, mf2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m1, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m2, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m4, ta, ma
+vle8ff.v v8, (a0)
+vsetvli zero, zero, e8, m8, ta, ma
+vle8ff.v v8, (a0)
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, mf2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m1, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m2, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m4, ta, ma
+vle16ff.v v8, (a0)
+vsetvli zero, zero, e16, m8, ta, ma
+vle16ff.v v8, (a0)
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m1, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m2, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m4, ta, ma
+vle32ff.v v8, (a0)
+vsetvli zero, zero, e32, m8, ta, ma
+vle32ff.v v8, (a0)
+
+vsetvli zero, zero, e64, m1, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m2, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m4, ta, ma
+vle64ff.v v8, (a0)
+vsetvli zero, zero, e64, m8, ta, ma
+vle64ff.v v8, (a0)
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 160
+# CHECK-NEXT: Total Cycles: 52
+# CHECK-NEXT: Total uOps: 160
+
+# CHECK: Dispatch Width: 8
+# CHECK-NEXT: uOps Per Cycle: 3.08
+# CHECK-NEXT: IPC: 3.08
+# CHECK-NEXT: Block RThroughput: 40.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vle64ff.v v8, (a0)
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFPA
+# CHECK-NEXT: [1] - AscalonFPB
+# CHECK-NEXT: [2] - AscalonFXA
+# CHECK-NEXT: [3] - AscalonFXB
+# CHECK-NEXT: [4.0] - AscalonFXC
+# CHECK-NEXT: [4.1] - AscalonFXC
+# CHECK-NEXT: [5.0] - AscalonFXD
+# CHECK-NEXT: [5.1] - AscalonFXD
+# CHECK-NEXT: [6.0] - AscalonLS
+# CHECK-NEXT: [6.1] - AscalonLS
+# CHECK-NEXT: [6.2] - AscalonLS
+# CHECK-NEXT: [7] - AscalonVA
+# CHECK-NEXT: [8] - AscalonVB
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
+# CHECK-NEXT: - - - - - - - - 26.00 27.00 27.00 40.00 40.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle16.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle64.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vse8.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vse16.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vse16.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vse16.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vse64.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vse64.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vse64.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vse64.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle64ff.v v8, (a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
new file mode 100644
index 0000000000000..e6f6313531b7a
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
@@ -0,0 +1,316 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vlse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vlse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vlse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vlse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vlse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vlse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vlse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vlse64.v v8, (a0), t0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m1, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m2, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m4, ta, ma
+vsse8.v v8, (a0), t0
+vsetvli zero, zero, e8, m8, ta, ma
+vsse8.v v8, (a0), t0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m1, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m2, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m4, ta, ma
+vsse16.v v8, (a0), t0
+vsetvli zero, zero, e16, m8, ta, ma
+vsse16.v v8, (a0), t0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m1, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m2, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m4, ta, ma
+vsse32.v v8, (a0), t0
+vsetvli zero, zero, e32, m8, ta, ma
+vsse32.v v8, (a0), t0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m2, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m4, ta, ma
+vsse64.v v8, (a0), t0
+vsetvli zero, zero, e64, m8, ta, ma
+vsse64.v v8, (a0), t0
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 88
+# CHECK-NEXT: Total Cycles: 53
+# CHECK-NEXT: Total uOps: 88
+
+# CHECK: Dispatch Width: 8
+# CHECK-NEXT: uOps Per Cycle: 1.66
+# CHECK-NEXT: IPC: 1.66
+# CHECK-NEXT: Block RThroughput: 22.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vsse64.v v8, (a0), t0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFPA
+# CHECK-NEXT: [1] - AscalonFPB
+# CHECK-NEXT: [2] - AscalonFXA
+# CHECK-NEXT: [3] - AscalonFXB
+# CHECK-NEXT: [4.0] - AscalonFXC
+# CHECK-NEXT: [4.1] - AscalonFXC
+# CHECK-NEXT: [5.0] - AscalonFXD
+# CHECK-NEXT: [5.1] - AscalonFXD
+# CHECK-NEXT: [6.0] - AscalonLS
+# CHECK-NEXT: [6.1] - AscalonLS
+# CHECK-NEXT: [6.2] - AscalonLS
+# CHECK-NEXT: [7] - AscalonVA
+# CHECK-NEXT: [8] - AscalonVB
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
+# CHECK-NEXT: - - - - - - - - 14.00 15.00 15.00 22.00 22.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse64.v v8, (a0), t0
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
new file mode 100644
index 0000000000000..6f2070cd75ced
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
@@ -0,0 +1,4727 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vlseg2e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vlseg2e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vlseg2e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vlseg2e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg3e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg3e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg3e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg3e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vlseg4e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vlseg4e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vlseg4e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vlseg4e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg5e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg5e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg5e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg5e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg6e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg6e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg6e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg6e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg6e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg7e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg7e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg7e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg7e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg7e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg7e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg7e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vlseg8e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vlseg8e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vlseg8e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vlseg8e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vlseg8e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vlseg8e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vlseg8e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e8, m4, tu, mu
+vsseg2e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e16, m4, tu, mu
+vsseg2e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e32, m4, tu, mu
+vsseg2e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsseg2e64.v v8,(a0)
+vsetvli zero, zero, e64, m4, tu, mu
+vsseg2e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsseg3e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsseg3e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg3e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsseg3e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg3e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsseg3e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e8, m2, tu, mu
+vsseg4e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e16, m2, tu, mu
+vsseg4e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg4e32.v v8,(a0)
+vsetvli zero, zero, e32, m2, tu, mu
+vsseg4e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg4e64.v v8,(a0)
+vsetvli zero, zero, e64, m2, tu, mu
+vsseg4e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg5e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg5e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg5e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg5e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg5e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg5e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg6e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg6e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
+vsseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, mf2, tu, mu
+vsseg6e16.v v8,(a0)
+vsetvli zero, zero, e16, m1, tu, mu
+vsseg6e16.v v8,(a0)
+vsetvli zero, zero, e32, mf2, tu, mu
+vsseg6e32.v v8,(a0)
+vsetvli zero, zero, e32, m1, tu, mu
+vsseg6e32.v v8,(a0)
+vsetvli zero, zero, e64, m1, tu, mu
+vsseg6e64.v v8,(a0)
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vsseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, mf4, tu, mu
+vsseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, mf2, tu, mu
+vsseg7e8.v v8,(a0)
+vsetvli zero, zero, e8, m1, tu, mu
+vsseg7e8.v v8,(a0)
+vsetvli zero, zero, e16, mf4, tu, mu
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+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e8, m1, tu, mu
+vsoxseg8ei8.v v8, (a0), v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e16, m1, tu, mu
+vsoxseg8ei16.v v8, (a0), v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e32, m1, tu, mu
+vsoxseg8ei32.v v8, (a0), v16
+vsetvli zero, zero, e64, m1, tu, mu
+vsoxseg8ei64.v v8, (a0), v16
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 1540
+# CHECK-NEXT: Total Cycles: 631
+# CHECK-NEXT: Total uOps: 1540
+
+# CHECK: Dispatch Width: 8
+# CHECK-NEXT: uOps Per Cycle: 2.44
+# CHECK-NEXT: IPC: 2.44
+# CHECK-NEXT: Block RThroughput: 385.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.33 * vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.33 * vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.33 * vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.33 * vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 128 0.33 * vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 128 0.33 * vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 128 0.33 * vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 128 0.33 * vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 128 0.33 * vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * vsoxseg8ei64.v v8, (a0), v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFPA
+# CHECK-NEXT: [1] - AscalonFPB
+# CHECK-NEXT: [2] - AscalonFXA
+# CHECK-NEXT: [3] - AscalonFXB
+# CHECK-NEXT: [4.0] - AscalonFXC
+# CHECK-NEXT: [4.1] - AscalonFXC
+# CHECK-NEXT: [5.0] - AscalonFXD
+# CHECK-NEXT: [5.1] - AscalonFXD
+# CHECK-NEXT: [6.0] - AscalonLS
+# CHECK-NEXT: [6.1] - AscalonLS
+# CHECK-NEXT: [6.2] - AscalonLS
+# CHECK-NEXT: [7] - AscalonVA
+# CHECK-NEXT: [8] - AscalonVB
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
+# CHECK-NEXT: - - - - - - - - 293.00 293.00 294.00 385.00 385.00
+
+# CHECK: Resource pressure by instruction:
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+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxseg8ei64.v v8, (a0), v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
new file mode 100644
index 0000000000000..db3cb1492cebe
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
@@ -0,0 +1,588 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vluxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vluxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vluxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vluxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vluxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vluxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vluxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vluxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vloxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vloxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vloxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vloxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vloxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vloxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vloxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vloxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsuxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsuxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsuxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsuxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsuxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsuxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsuxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsuxei64.v v8, (a0), v0
+
+vsetvli zero, zero, e8, mf8, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, mf2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m1, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m2, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m4, ta, ma
+vsoxei8.v v8, (a0), v0
+vsetvli zero, zero, e8, m8, ta, ma
+vsoxei8.v v8, (a0), v0
+
+vsetvli zero, zero, e16, mf4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, mf2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m1, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m2, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m4, ta, ma
+vsoxei16.v v8, (a0), v0
+vsetvli zero, zero, e16, m8, ta, ma
+vsoxei16.v v8, (a0), v0
+
+vsetvli zero, zero, e32, mf2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m1, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m2, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m4, ta, ma
+vsoxei32.v v8, (a0), v0
+vsetvli zero, zero, e32, m8, ta, ma
+vsoxei32.v v8, (a0), v0
+
+vsetvli zero, zero, e64, m1, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m2, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m4, ta, ma
+vsoxei64.v v8, (a0), v0
+vsetvli zero, zero, e64, m8, ta, ma
+vsoxei64.v v8, (a0), v0
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 176
+# CHECK-NEXT: Total Cycles: 72
+# CHECK-NEXT: Total uOps: 176
+
+# CHECK: Dispatch Width: 8
+# CHECK-NEXT: uOps Per Cycle: 2.44
+# CHECK-NEXT: IPC: 2.44
+# CHECK-NEXT: Block RThroughput: 44.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * vsoxei64.v v8, (a0), v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFPA
+# CHECK-NEXT: [1] - AscalonFPB
+# CHECK-NEXT: [2] - AscalonFXA
+# CHECK-NEXT: [3] - AscalonFXB
+# CHECK-NEXT: [4.0] - AscalonFXC
+# CHECK-NEXT: [4.1] - AscalonFXC
+# CHECK-NEXT: [5.0] - AscalonFXD
+# CHECK-NEXT: [5.1] - AscalonFXD
+# CHECK-NEXT: [6.0] - AscalonLS
+# CHECK-NEXT: [6.1] - AscalonLS
+# CHECK-NEXT: [6.2] - AscalonLS
+# CHECK-NEXT: [7] - AscalonVA
+# CHECK-NEXT: [8] - AscalonVB
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
+# CHECK-NEXT: - - - - - - - - 29.00 29.00 30.00 44.00 44.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vluxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsoxei64.v v8, (a0), v0
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
new file mode 100644
index 0000000000000..566179e435680
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
@@ -0,0 +1,893 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, mf8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, mf8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, mf4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, mf8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, mf4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, mf2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vmv1r.v v8, v16
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, mf8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, mf8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, mf4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, mf8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, mf4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, mf2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vmv2r.v v8, v16
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, mf8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, mf8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, mf4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, mf8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, mf4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, mf2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vmv4r.v v8, v16
+vsetvli zero, zero, e8, mf8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, mf4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, mf2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e8, m8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, mf8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, mf4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, mf2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e16, m8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, mf8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, mf4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, mf2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e32, m8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, mf8, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, mf4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, mf2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m1, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m2, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m4, tu, mu
+vmv8r.v v8, v16
+vsetvli zero, zero, e64, m8, tu, mu
+vmv8r.v v8, v16
+
+vsetvli zero, zero, e64, m1, tu, mu
+vmv.s.x v8, x5
+vmv.x.s x7, v16
+
+vsetvli zero, zero, e64, m2, tu, mu
+vmv.s.x v8, x5
+vmv.x.s x7, v16
+
+vsetvli zero, zero, e64, m4, tu, mu
+vmv.s.x v8, x5
+vmv.x.s x7, v16
+
+vsetvli zero, zero, e64, m8, tu, mu
+vmv.s.x v8, x5
+vmv.x.s x7, v16
+
+vsetvli zero, zero, e64, m1, tu, mu
+vfmv.s.f v8, f5
+vfmv.f.s f7, v16
+
+vsetvli zero, zero, e64, m2, tu, mu
+vfmv.s.f v8, f5
+vfmv.f.s f7, v16
+
+vsetvli zero, zero, e64, m4, tu, mu
+vfmv.s.f v8, f5
+vfmv.f.s f7, v16
+
+vsetvli zero, zero, e64, m8, tu, mu
+vfmv.s.f v8, f5
+vfmv.f.s f7, v16
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 280
+# CHECK-NEXT: Total Cycles: 327
+# CHECK-NEXT: Total uOps: 280
+
+# CHECK: Dispatch Width: 8
+# CHECK-NEXT: uOps Per Cycle: 0.86
+# CHECK-NEXT: IPC: 0.86
+# CHECK-NEXT: Block RThroughput: 324.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv.s.x v8, t0
+# CHECK-NEXT: 1 2 1.00 vmv.x.s t2, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv.s.x v8, t0
+# CHECK-NEXT: 1 2 1.00 vmv.x.s t2, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv.s.x v8, t0
+# CHECK-NEXT: 1 2 1.00 vmv.x.s t2, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vmv.s.x v8, t0
+# CHECK-NEXT: 1 2 1.00 vmv.x.s t2, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 vfmv.s.f v8, ft5
+# CHECK-NEXT: 1 2 1.00 vfmv.f.s ft7, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vfmv.s.f v8, ft5
+# CHECK-NEXT: 1 2 1.00 vfmv.f.s ft7, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 vfmv.s.f v8, ft5
+# CHECK-NEXT: 1 2 1.00 vfmv.f.s ft7, v16
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 vfmv.s.f v8, ft5
+# CHECK-NEXT: 1 2 1.00 vfmv.f.s ft7, v16
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFPA
+# CHECK-NEXT: [1] - AscalonFPB
+# CHECK-NEXT: [2] - AscalonFXA
+# CHECK-NEXT: [3] - AscalonFXB
+# CHECK-NEXT: [4.0] - AscalonFXC
+# CHECK-NEXT: [4.1] - AscalonFXC
+# CHECK-NEXT: [5.0] - AscalonFXD
+# CHECK-NEXT: [5.1] - AscalonFXD
+# CHECK-NEXT: [6.0] - AscalonLS
+# CHECK-NEXT: [6.1] - AscalonLS
+# CHECK-NEXT: [6.2] - AscalonLS
+# CHECK-NEXT: [7] - AscalonVA
+# CHECK-NEXT: [8] - AscalonVB
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
+# CHECK-NEXT: - - 2.00 2.00 4.00 4.00 2.00 2.00 - - - 324.00 324.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - - 8.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 8.00 - vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 2.00 - vmv.s.x v8, t0
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 2.00 vmv.x.s t2, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - - 2.00 vmv.s.x v8, t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - 2.00 - vmv.x.s t2, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vmv.s.x v8, t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 2.00 vmv.x.s t2, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - 1.00 - - - - - - - - 2.00 vmv.s.x v8, t0
+# CHECK-NEXT: - - 1.00 - - - - - - - - 2.00 - vmv.x.s t2, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 2.00 - vfmv.s.f v8, ft5
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 2.00 vfmv.f.s ft7, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - - 2.00 vfmv.s.f v8, ft5
+# CHECK-NEXT: - - - - 1.00 - - - - - - 2.00 - vfmv.f.s ft7, v16
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vfmv.s.f v8, ft5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 2.00 vfmv.f.s ft7, v16
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - 1.00 - - - - - - - 2.00 - vfmv.s.f v8, ft5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - 2.00 vfmv.f.s ft7, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
new file mode 100644
index 0000000000000..558e6ac267965
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
@@ -0,0 +1,436 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+
+# Simple integer reductions: varies by LMUL
+vsetvli zero, zero, e32, m1, tu, mu
+vredsum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vredsum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vredsum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vredsum.vs v5, v7, v8
+
+# Advanced integer reductions: varies by LMUL and SEW
+vsetvli zero, zero, e16, m1, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m2, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m4, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m8, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m1, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m2, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m4, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m8, tu, mu
+vredmin.vs v5, v7, v8
+vredmax.vs v5, v7, v8
+
+# Simple floating point reductions: varies by LMUL and SEW
+vsetvli zero, zero, e16, m1, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m2, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m4, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m8, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m1, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m2, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m4, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m8, tu, mu
+vfredusum.vs v5, v7, v8
+vfredosum.vs v5, v7, v8
+
+# Advanced floating point reductions: varies by LMUL and SEW
+vsetvli zero, zero, e16, m1, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m2, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m4, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e16, m8, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m1, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m2, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m4, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e32, m8, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m1, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m2, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m4, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+vsetvli zero, zero, e64, m8, tu, mu
+vfredmin.vs v5, v7, v8
+vfredmax.vs v5, v7, v8
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 116
+# CHECK-NEXT: Total Cycles: 563
+# CHECK-NEXT: Total uOps: 116
+
+# CHECK: Dispatch Width: 8
+# CHECK-NEXT: uOps Per Cycle: 0.21
+# CHECK-NEXT: IPC: 0.21
+# CHECK-NEXT: Block RThroughput: 545.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vredsum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vredsum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vredsum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vredsum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 2 1.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 2 1.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 2 1.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 18 9.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 36 18.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 72 36.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 144 72.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 18 9.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 36 18.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 72 36.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 144 72.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 18 9.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 36 18.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 72 36.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 144 72.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 2 1.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 2 1.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 2 1.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 vfredmax.vs v5, v7, v8
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFPA
+# CHECK-NEXT: [1] - AscalonFPB
+# CHECK-NEXT: [2] - AscalonFXA
+# CHECK-NEXT: [3] - AscalonFXB
+# CHECK-NEXT: [4.0] - AscalonFXC
+# CHECK-NEXT: [4.1] - AscalonFXC
+# CHECK-NEXT: [5.0] - AscalonFXD
+# CHECK-NEXT: [5.1] - AscalonFXD
+# CHECK-NEXT: [6.0] - AscalonLS
+# CHECK-NEXT: [6.1] - AscalonLS
+# CHECK-NEXT: [6.2] - AscalonLS
+# CHECK-NEXT: [7] - AscalonVA
+# CHECK-NEXT: [8] - AscalonVB
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
+# CHECK-NEXT: - - 3.00 3.00 30.00 30.00 5.00 5.00 - - - 530.00 560.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 1.00 vredsum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 2.00 vredsum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 4.00 vredsum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - 1.00 - - - - 8.00 - vredsum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - - 1.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 1.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 2.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - 1.00 - - - - - - - - 4.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - 4.00 - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 8.00 - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 8.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - - 1.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 1.00 - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 2.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - 1.00 - - - - - - - - 4.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - 4.00 - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 8.00 - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 8.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - - 1.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 1.00 - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 2.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - 1.00 - - - - - - - - 4.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - 4.00 - vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - 8.00 - vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 8.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - - 1.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 18.00 - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - - 2.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 36.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 4.00 - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 72.00 - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - - 8.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 144.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 18.00 - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 36.00 - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 4.00 - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 72.00 - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - - 8.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 144.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 18.00 - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 36.00 - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 4.00 - vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 72.00 - vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - - 8.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 144.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 1.00 - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 2.00 - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 4.00 - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 4.00 - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 8.00 - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 8.00 - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 1.00 - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 2.00 - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 4.00 - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 4.00 - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 8.00 - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 8.00 - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 1.00 - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 2.00 - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 4.00 - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 4.00 - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 8.00 - vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 8.00 - vfredmax.vs v5, v7, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
new file mode 100644
index 0000000000000..f59b7aec7d043
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
@@ -0,0 +1,84 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e32, m1, tu, mu
+vrgather.vv v5, v7, v8
+vcompress.vm v4, v9, v0
+
+vsetvli zero, zero, e32, m2, tu, mu
+vrgather.vv v5, v7, v8
+vcompress.vm v4, v9, v0
+
+vsetvli zero, zero, e32, m4, tu, mu
+vrgather.vv v5, v7, v8
+vcompress.vm v4, v9, v0
+
+vsetvli zero, zero, e32, m8, tu, mu
+vrgather.vv v5, v7, v8
+vcompress.vm v4, v9, v0
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 12
+# CHECK-NEXT: Total Cycles: 77
+# CHECK-NEXT: Total uOps: 12
+
+# CHECK: Dispatch Width: 8
+# CHECK-NEXT: uOps Per Cycle: 0.16
+# CHECK-NEXT: IPC: 0.16
+# CHECK-NEXT: Block RThroughput: 72.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 1.50 vrgather.vv v5, v7, v8
+# CHECK-NEXT: 1 5 1.50 vcompress.vm v4, v9, v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 7 2.50 vrgather.vv v5, v7, v8
+# CHECK-NEXT: 1 7 2.50 vcompress.vm v4, v9, v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 15 6.50 vrgather.vv v5, v7, v8
+# CHECK-NEXT: 1 15 6.50 vcompress.vm v4, v9, v0
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 51 24.50 vrgather.vv v5, v7, v8
+# CHECK-NEXT: 1 51 24.50 vcompress.vm v4, v9, v0
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFPA
+# CHECK-NEXT: [1] - AscalonFPB
+# CHECK-NEXT: [2] - AscalonFXA
+# CHECK-NEXT: [3] - AscalonFXB
+# CHECK-NEXT: [4.0] - AscalonFXC
+# CHECK-NEXT: [4.1] - AscalonFXC
+# CHECK-NEXT: [5.0] - AscalonFXD
+# CHECK-NEXT: [5.1] - AscalonFXD
+# CHECK-NEXT: [6.0] - AscalonLS
+# CHECK-NEXT: [6.1] - AscalonLS
+# CHECK-NEXT: [6.2] - AscalonLS
+# CHECK-NEXT: [7] - AscalonVA
+# CHECK-NEXT: [8] - AscalonVB
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
+# CHECK-NEXT: - - 1.00 1.00 2.00 2.00 1.00 1.00 - - - 72.00 72.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 3.00 vrgather.vv v5, v7, v8
+# CHECK-NEXT: - - - - - - 1.00 - - - - 3.00 - vcompress.vm v4, v9, v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - 5.00 - vrgather.vv v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 5.00 vcompress.vm v4, v9, v0
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - 1.00 - - - - - - 13.00 vrgather.vv v5, v7, v8
+# CHECK-NEXT: - - - - 1.00 - - - - - - 13.00 - vcompress.vm v4, v9, v0
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - 1.00 - - - - - - - - 49.00 vrgather.vv v5, v7, v8
+# CHECK-NEXT: - - 1.00 - - - - - - - - 49.00 - vcompress.vm v4, v9, v0
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
new file mode 100644
index 0000000000000..095d03441fbb0
--- /dev/null
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
@@ -0,0 +1,130 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+
+vsetvli zero, zero, e32, m1, ta, ma
+
+vsll.vv v1, v2, v5
+vsll.vx v1, v2, t0
+vsll.vi v1, v2, 7
+
+vsrl.vv v1, v2, v5
+vsrl.vx v1, v2, t0
+vsrl.vi v1, v2, 7
+
+vsra.vv v1, v2, v5
+vsra.vx v1, v2, t0
+vsra.vi v1, v2, 7
+
+vsetvli zero, zero, e32, mf4, ta, ma
+
+vsll.vv v1, v2, v5
+vsll.vx v1, v2, t0
+vsll.vi v1, v2, 7
+
+vsrl.vv v1, v2, v5
+vsrl.vx v1, v2, t0
+vsrl.vi v1, v2, 7
+
+vsra.vv v1, v2, v5
+vsra.vx v1, v2, t0
+vsra.vi v1, v2, 7
+
+vsetvli zero, zero, e32, m8, ta, ma
+
+vmul.vv v1, v2, v5
+vmul.vx v1, v2, t1
+
+vmadd.vv v1, v2, v5
+vmadd.vx v1, t1, v2
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 25
+# CHECK-NEXT: Total Cycles: 38
+# CHECK-NEXT: Total uOps: 25
+
+# CHECK: Dispatch Width: 8
+# CHECK-NEXT: uOps Per Cycle: 0.66
+# CHECK-NEXT: IPC: 0.66
+# CHECK-NEXT: Block RThroughput: 26.5
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects (U)
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 0.50 vsll.vv v1, v2, v5
+# CHECK-NEXT: 1 1 0.50 vsll.vx v1, v2, t0
+# CHECK-NEXT: 1 1 0.50 vsll.vi v1, v2, 7
+# CHECK-NEXT: 1 1 0.50 vsrl.vv v1, v2, v5
+# CHECK-NEXT: 1 1 0.50 vsrl.vx v1, v2, t0
+# CHECK-NEXT: 1 1 0.50 vsrl.vi v1, v2, 7
+# CHECK-NEXT: 1 1 0.50 vsra.vv v1, v2, v5
+# CHECK-NEXT: 1 1 0.50 vsra.vx v1, v2, t0
+# CHECK-NEXT: 1 1 0.50 vsra.vi v1, v2, 7
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.50 vsll.vv v1, v2, v5
+# CHECK-NEXT: 1 1 0.50 vsll.vx v1, v2, t0
+# CHECK-NEXT: 1 1 0.50 vsll.vi v1, v2, 7
+# CHECK-NEXT: 1 1 0.50 vsrl.vv v1, v2, v5
+# CHECK-NEXT: 1 1 0.50 vsrl.vx v1, v2, t0
+# CHECK-NEXT: 1 1 0.50 vsrl.vi v1, v2, 7
+# CHECK-NEXT: 1 1 0.50 vsra.vv v1, v2, v5
+# CHECK-NEXT: 1 1 0.50 vsra.vx v1, v2, t0
+# CHECK-NEXT: 1 1 0.50 vsra.vi v1, v2, 7
+# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 4.00 vmul.vv v1, v2, v5
+# CHECK-NEXT: 1 8 4.00 vmul.vx v1, v2, t1
+# CHECK-NEXT: 1 8 4.00 vmadd.vv v1, v2, v5
+# CHECK-NEXT: 1 8 4.00 vmadd.vx v1, t1, v2
+
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFPA
+# CHECK-NEXT: [1] - AscalonFPB
+# CHECK-NEXT: [2] - AscalonFXA
+# CHECK-NEXT: [3] - AscalonFXB
+# CHECK-NEXT: [4.0] - AscalonFXC
+# CHECK-NEXT: [4.1] - AscalonFXC
+# CHECK-NEXT: [5.0] - AscalonFXD
+# CHECK-NEXT: [5.1] - AscalonFXD
+# CHECK-NEXT: [6.0] - AscalonLS
+# CHECK-NEXT: [6.1] - AscalonLS
+# CHECK-NEXT: [6.2] - AscalonLS
+# CHECK-NEXT: [7] - AscalonVA
+# CHECK-NEXT: [8] - AscalonVB
+
+# CHECK: Resource pressure per iteration:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
+# CHECK-NEXT: - - 3.00 3.00 3.00 3.00 5.00 5.00 - - - 26.00 27.00
+
+# CHECK: Resource pressure by instruction:
+# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
+# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 1.00 vsll.vv v1, v2, v5
+# CHECK-NEXT: - - - - - - 1.00 - - - - 1.00 - vsll.vx v1, v2, t0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 1.00 vsll.vi v1, v2, 7
+# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vsrl.vv v1, v2, v5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 1.00 vsrl.vx v1, v2, t0
+# CHECK-NEXT: - - - 1.00 - - - - - - - 1.00 - vsrl.vi v1, v2, 7
+# CHECK-NEXT: - - 1.00 - - - - - - - - - 1.00 vsra.vv v1, v2, v5
+# CHECK-NEXT: - - - - - - 1.00 - - - - 1.00 - vsra.vx v1, v2, t0
+# CHECK-NEXT: - - - - - - - 1.00 - - - - 1.00 vsra.vi v1, v2, 7
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf4, ta, ma
+# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vsll.vv v1, v2, v5
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 1.00 vsll.vx v1, v2, t0
+# CHECK-NEXT: - - - 1.00 - - - - - - - - 1.00 vsll.vi v1, v2, 7
+# CHECK-NEXT: - - 1.00 - - - - - - - - 1.00 - vsrl.vv v1, v2, v5
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 1.00 vsrl.vx v1, v2, t0
+# CHECK-NEXT: - - - - - - - 1.00 - - - 1.00 - vsrl.vi v1, v2, 7
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 1.00 vsra.vv v1, v2, v5
+# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vsra.vx v1, v2, t0
+# CHECK-NEXT: - - - - 1.00 - - - - - - - 1.00 vsra.vi v1, v2, 7
+# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - 1.00 - - - - - - - 8.00 - vmul.vv v1, v2, v5
+# CHECK-NEXT: - - 1.00 - - - - - - - - - 8.00 vmul.vx v1, v2, t1
+# CHECK-NEXT: - - - - - - - 1.00 - - - 8.00 - vmadd.vv v1, v2, v5
+# CHECK-NEXT: - - - - - - 1.00 - - - - - 8.00 vmadd.vx v1, t1, v2
>From 863b8e1921bb4e0f84de2acd1f2094e1bc973597 Mon Sep 17 00:00:00 2001
From: Petr Penzin <ppenzin at tenstorrent.com>
Date: Tue, 18 Nov 2025 02:10:07 -0600
Subject: [PATCH 9/9] Review feedback
Remove redundant latencies of 1. Use `-instruction-tables=full` in
llvm-mca test command lines.
---
.../lib/Target/RISCV/RISCVSchedTTAscalonD8.td | 35 +-
.../llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s | 1311 ++--
.../llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s | 105 +-
.../RISCV/tt-ascalon-d8/vle-vse-vlm.s | 671 +-
.../llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s | 383 +-
.../RISCV/tt-ascalon-d8/vlseg-vsseg.s | 6191 +++++++++--------
.../llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s | 735 +-
.../tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s | 1151 +--
.../llvm-mca/RISCV/tt-ascalon-d8/vreduce.s | 497 +-
.../RISCV/tt-ascalon-d8/vrgather-vcompress.s | 79 +-
.../RISCV/tt-ascalon-d8/vshift-vmul.s | 133 +-
11 files changed, 5676 insertions(+), 5615 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
index cc5b75621fa2e..5dcbd52e12ac0 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedTTAscalonD8.td
@@ -414,12 +414,10 @@ def : ReadAdvance<ReadSingleBitImm, 0>;
def : WriteRes<WriteRdVLENB, [AscalonFXA]>;
// Configuration-Setting Instructions
-let Latency = 1 in {
def : WriteRes<WriteVSETVLI, [AscalonV]>;
def : WriteRes<WriteVSETIVLI, [AscalonV]>;
-}
let Latency = 2 in {
-def : WriteRes<WriteVSETVL, [AscalonV]>;
+ def : WriteRes<WriteVSETVL, [AscalonV]>;
}
// Vector Loads and Stores
@@ -430,15 +428,12 @@ foreach mx = SchedMxList in {
defm "" : LMULWriteResMX<"WriteVLDE", [AscalonLS], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVLDFF", [AscalonLS], mx, IsWorstCase>;
}
- let Latency = 1 in
defm "" : LMULWriteResMX<"WriteVSTE", [AscalonLS], mx, IsWorstCase>;
}
foreach mx = SchedMxList in {
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 1 in
defm "" : LMULWriteResMX<"WriteVLDM", [AscalonLS], mx, IsWorstCase>;
- let Latency = 1 in
defm "" : LMULWriteResMX<"WriteVSTM", [AscalonLS], mx, IsWorstCase>;
}
@@ -491,18 +486,16 @@ foreach mx = ["M1", "M2", "M4", "M8"] in {
}
}
-let Latency = 1 in {
- // VLD*R is LMUL aware
- def : WriteRes<WriteVLD1R, [AscalonLS]>;
- def : WriteRes<WriteVLD2R, [AscalonLS]>;
- def : WriteRes<WriteVLD4R, [AscalonLS]>;
- def : WriteRes<WriteVLD8R, [AscalonLS]>;
- // VST*R is LMUL aware
- def : WriteRes<WriteVST1R, [AscalonLS]>;
- def : WriteRes<WriteVST2R, [AscalonLS]>;
- def : WriteRes<WriteVST4R, [AscalonLS]>;
- def : WriteRes<WriteVST8R, [AscalonLS]>;
-}
+// VLD*R is LMUL aware
+def : WriteRes<WriteVLD1R, [AscalonLS]>;
+def : WriteRes<WriteVLD2R, [AscalonLS]>;
+def : WriteRes<WriteVLD4R, [AscalonLS]>;
+def : WriteRes<WriteVLD8R, [AscalonLS]>;
+// VST*R is LMUL aware
+def : WriteRes<WriteVST1R, [AscalonLS]>;
+def : WriteRes<WriteVST2R, [AscalonLS]>;
+def : WriteRes<WriteVST4R, [AscalonLS]>;
+def : WriteRes<WriteVST8R, [AscalonLS]>;
// Segmented Loads and Stores
foreach mx = SchedMxList in {
@@ -832,10 +825,8 @@ foreach mx = SchedMxListFWRed in {
// Vector Mask Instructions
foreach mx = SchedMxList in {
defvar IsWorstCase = AscalonIsWorstCaseMX<mx, SchedMxList>.c;
- let Latency = 1 in {
- defm "" : LMULWriteResMX<"WriteVMALUV", [AscalonV], mx, IsWorstCase>;
- defm "" : LMULWriteResMX<"WriteVMSFSV", [AscalonV], mx, IsWorstCase>;
- }
+ defm "" : LMULWriteResMX<"WriteVMALUV", [AscalonV], mx, IsWorstCase>;
+ defm "" : LMULWriteResMX<"WriteVMSFSV", [AscalonV], mx, IsWorstCase>;
let Latency = 2, ReleaseAtCycles = [1, 2] in {
defm "" : LMULWriteResMX<"WriteVMPopV", [AscalonFX, AscalonV], mx, IsWorstCase>;
defm "" : LMULWriteResMX<"WriteVMFFSV", [AscalonFX, AscalonV], mx, IsWorstCase>;
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
index e970391adb63e..53711ed515663 100644
--- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vdiv_vsqrt.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s
vsetvli zero, zero, e8, mf8, tu, mu
vdiv.vv v8, v16, v24
@@ -326,15 +326,19 @@ vfsqrt.v v8, v16
vsetvli zero, zero, e64, m8, tu, mu
vfsqrt.v v8, v16
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 320
-# CHECK-NEXT: Total Cycles: 2382
-# CHECK-NEXT: Total uOps: 320
-
-# CHECK: Dispatch Width: 8
-# CHECK-NEXT: uOps Per Cycle: 0.13
-# CHECK-NEXT: IPC: 0.13
-# CHECK-NEXT: Block RThroughput: 2359.5
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB
+# CHECK-NEXT: [1] - AscalonFPA:1
+# CHECK-NEXT: [2] - AscalonFPB:1
+# CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD
+# CHECK-NEXT: [4] - AscalonFXA:1
+# CHECK-NEXT: [5] - AscalonFXB:1
+# CHECK-NEXT: [6] - AscalonFXC:2
+# CHECK-NEXT: [7] - AscalonFXD:2
+# CHECK-NEXT: [8] - AscalonLS:3
+# CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB
+# CHECK-NEXT: [10] - AscalonVA:1
+# CHECK-NEXT: [11] - AscalonVB:1
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -343,328 +347,331 @@ vfsqrt.v v8, v16
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 7 3.50 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 7 3.50 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 7 3.50 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 7 3.50 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 7 3.50 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 14 7.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 28 14.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 6 3.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 6 3.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 6 3.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 6 3.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 12 6.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 24 12.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 5 2.50 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 5 2.50 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 5 2.50 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 10 5.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 20 10.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 40 20.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 8.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 32 16.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 64 32.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 7 3.50 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 7 3.50 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 7 3.50 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 7 3.50 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 7 3.50 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 14 7.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 28 14.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 6 3.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 6 3.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 6 3.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 6 3.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 12 6.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 24 12.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 5 2.50 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 5 2.50 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 5 2.50 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 10 5.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 20 10.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 40 20.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 56 28.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 8.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 32 16.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 64 32.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 12 6.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 24 12.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 5 2.50 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 5 2.50 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 5 2.50 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 10 5.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 20 10.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 40 20.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 8.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 32 16.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 64 32.00 vfdiv.vv v8, v16, v24
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 12 6.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 24 12.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 5 2.50 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 5 2.50 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 5 2.50 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 10 5.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 20 10.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 40 20.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 8.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 32 16.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 64 32.00 vfdiv.vf v8, v16, fa0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 6 3.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 12 6.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 24 12.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 5 2.50 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 5 2.50 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 5 2.50 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 10 5.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 20 10.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 40 20.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 48 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 8.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 32 16.00 vfsqrt.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 64 32.00 vfsqrt.v v8, v16
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 3.50 7 AscalonFX,AscalonV[7] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 3.50 7 AscalonFX,AscalonV[7] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 3.50 7 AscalonFX,AscalonV[7] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 3.50 7 AscalonFX,AscalonV[7] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 3.50 7 AscalonFX,AscalonV[7] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 14 7.00 14 AscalonFX,AscalonV[14] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 28 14.00 28 AscalonFX,AscalonV[28] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFX,AscalonV[6] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFX,AscalonV[6] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFX,AscalonV[6] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFX,AscalonV[6] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 12 AscalonFX,AscalonV[12] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 12.00 24 AscalonFX,AscalonV[24] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFX,AscalonV[48] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFX,AscalonV[5] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFX,AscalonV[5] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFX,AscalonV[5] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 AscalonFX,AscalonV[10] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 20 10.00 20 AscalonFX,AscalonV[20] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 40 20.00 40 AscalonFX,AscalonV[40] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 AscalonFX,AscalonV[16] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 16.00 32 AscalonFX,AscalonV[32] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 64 32.00 64 AscalonFX,AscalonV[64] VDIV_VV vdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 7 3.50 7 AscalonFX,AscalonV[7] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 7 3.50 7 AscalonFX,AscalonV[7] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 7 3.50 7 AscalonFX,AscalonV[7] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 3.50 7 AscalonFX,AscalonV[7] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 7 3.50 7 AscalonFX,AscalonV[7] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 14 7.00 14 AscalonFX,AscalonV[14] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 28 14.00 28 AscalonFX,AscalonV[28] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFX,AscalonV[6] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFX,AscalonV[6] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFX,AscalonV[6] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFX,AscalonV[6] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 12 AscalonFX,AscalonV[12] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 12.00 24 AscalonFX,AscalonV[24] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFX,AscalonV[48] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFX,AscalonV[5] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFX,AscalonV[5] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFX,AscalonV[5] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 AscalonFX,AscalonV[10] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 20 10.00 20 AscalonFX,AscalonV[20] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 40 20.00 40 AscalonFX,AscalonV[40] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 56 28.00 56 AscalonFX,AscalonV[56] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 AscalonFX,AscalonV[16] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 16.00 32 AscalonFX,AscalonV[32] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 64 32.00 64 AscalonFX,AscalonV[64] VDIV_VX vdiv.vx v8, v16, a0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFP,AscalonV[6] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFP,AscalonV[6] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFP,AscalonV[6] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFP,AscalonV[6] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 12 AscalonFP,AscalonV[12] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 12.00 24 AscalonFP,AscalonV[24] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFP,AscalonV[5] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFP,AscalonV[5] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFP,AscalonV[5] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 AscalonFP,AscalonV[10] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 20 10.00 20 AscalonFP,AscalonV[20] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 40 20.00 40 AscalonFP,AscalonV[40] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFP,AscalonV[8] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFP,AscalonV[8] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 AscalonFP,AscalonV[16] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 16.00 32 AscalonFP,AscalonV[32] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 64 32.00 64 AscalonFP,AscalonV[64] VFDIV_VV vfdiv.vv v8, v16, v24
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFP,AscalonV[6] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFP,AscalonV[6] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFP,AscalonV[6] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFP,AscalonV[6] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 12 AscalonFP,AscalonV[12] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 12.00 24 AscalonFP,AscalonV[24] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFP,AscalonV[5] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFP,AscalonV[5] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFP,AscalonV[5] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 AscalonFP,AscalonV[10] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 20 10.00 20 AscalonFP,AscalonV[20] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 40 20.00 40 AscalonFP,AscalonV[40] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFP,AscalonV[8] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFP,AscalonV[8] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 AscalonFP,AscalonV[16] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 16.00 32 AscalonFP,AscalonV[32] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 64 32.00 64 AscalonFP,AscalonV[64] VFDIV_VF vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFP,AscalonV[6] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFP,AscalonV[6] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFP,AscalonV[6] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 6 3.00 6 AscalonFP,AscalonV[6] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 12 6.00 12 AscalonFP,AscalonV[12] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 24 12.00 24 AscalonFP,AscalonV[24] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFP,AscalonV[5] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFP,AscalonV[5] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 2.50 5 AscalonFP,AscalonV[5] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 10 5.00 10 AscalonFP,AscalonV[10] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 20 10.00 20 AscalonFP,AscalonV[20] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 40 20.00 40 AscalonFP,AscalonV[40] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 48 24.00 48 AscalonFP,AscalonV[48] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFP,AscalonV[8] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFP,AscalonV[8] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 8.00 16 AscalonFP,AscalonV[16] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 16.00 32 AscalonFP,AscalonV[32] VFSQRT_V vfsqrt.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 64 32.00 64 AscalonFP,AscalonV[64] VFSQRT_V vfsqrt.v v8, v16
# CHECK: Resources:
# CHECK-NEXT: [0] - AscalonFPA
@@ -683,327 +690,327 @@ vfsqrt.v v8, v16
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
-# CHECK-NEXT: 48.00 48.00 - - - - 32.00 32.00 - - - 2379.00 2340.00
+# CHECK-NEXT: 48.00 48.00 10.67 10.67 10.67 10.67 10.67 10.67 - - - 2359.50 2359.50
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 7.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - 7.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 7.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 7.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 7.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - 14.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 28.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - 56.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 56.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - 6.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 6.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - 6.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 6.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 12.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 24.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 48.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 56.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 56.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 5.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - 5.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 5.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - 10.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 20.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 40.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 56.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 56.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 56.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 8.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 8.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 16.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 32.00 vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - 64.00 - vdiv.vv v8, v16, v24
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 7.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 7.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 7.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 7.00 vdiv.vx v8, v16, a0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
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-# CHECK-NEXT: - 1.00 - - - - - - - - - - 6.00 vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1.00 - - - - - - - - - - 12.00 - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - 1.00 - - - - - - - - - - 24.00 vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1.00 - - - - - - - - - - 48.00 - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - 1.00 - - - - - - - - - - 48.00 vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1.00 - - - - - - - - - - 48.00 - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - 1.00 - - - - - - - - - - 5.00 vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1.00 - - - - - - - - - - - 5.00 vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - 1.00 - - - - - - - - - - 5.00 vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1.00 - - - - - - - - - - - 10.00 vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - 1.00 - - - - - - - - - - 20.00 vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1.00 - - - - - - - - - - 40.00 - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - 1.00 - - - - - - - - - - 48.00 vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1.00 - - - - - - - - - - 48.00 - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: - 1.00 - - - - - - - - - - 48.00 vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1.00 - - - - - - - - - - 8.00 - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - 1.00 - - - - - - - - - 8.00 - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1.00 - - - - - - - - - - 16.00 - vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - 1.00 - - - - - - - - - - 32.00 vfsqrt.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1.00 - - - - - - - - - - 64.00 - vfsqrt.v v8, v16
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 3.50 3.50 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 7.00 7.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 28.00 28.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf8, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 3.00 3.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 12.00 12.00 vdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf8, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf4, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf4, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 7.00 7.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 28.00 28.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf8, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf4, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 10.00 10.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 28.00 28.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 28.00 28.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 28.00 28.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 8.00 8.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 16.00 16.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 32.00 32.00 vdiv.vx v8, v16, a0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 3.00 3.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 3.00 3.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 3.00 3.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 3.00 3.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 6.00 6.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 12.00 12.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 2.50 2.50 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 2.50 2.50 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 2.50 2.50 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 5.00 5.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 10.00 10.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 20.00 20.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 4.00 4.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 4.00 4.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 8.00 8.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 16.00 16.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 32.00 32.00 vfdiv.vv v8, v16, v24
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 3.00 3.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 3.00 3.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 3.00 3.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 3.00 3.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 6.00 6.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 12.00 12.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 2.50 2.50 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 2.50 2.50 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 2.50 2.50 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 5.00 5.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 10.00 10.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 20.00 20.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 4.00 4.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 4.00 4.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 8.00 8.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 16.00 16.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 32.00 32.00 vfdiv.vf v8, v16, fa0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 3.00 3.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 3.00 3.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 3.00 3.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 3.00 3.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 6.00 6.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 12.00 12.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 2.50 2.50 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 2.50 2.50 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 2.50 2.50 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 5.00 5.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 10.00 10.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 20.00 20.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 24.00 24.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 4.00 4.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 4.00 4.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 8.00 8.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 16.00 16.00 vfsqrt.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 0.50 0.50 - - - - - - - - - 32.00 32.00 vfsqrt.v v8, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
index 8771f91f449db..d819922e114d0 100644
--- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vislide-vx.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s
vsetvli zero, zero, e32, m2, tu, mu
vslidedown.vx v5, v7, x6
@@ -28,15 +28,19 @@ vslideup.vx v5, v7, x6, v0.t
vsetvli zero, zero, e32, m8, tu, mu
vslideup.vx v5, v7, x6, v0.t
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 18
-# CHECK-NEXT: Total Cycles: 31
-# CHECK-NEXT: Total uOps: 18
-
-# CHECK: Dispatch Width: 8
-# CHECK-NEXT: uOps Per Cycle: 0.58
-# CHECK-NEXT: IPC: 0.58
-# CHECK-NEXT: Block RThroughput: 30.0
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB
+# CHECK-NEXT: [1] - AscalonFPA:1
+# CHECK-NEXT: [2] - AscalonFPB:1
+# CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD
+# CHECK-NEXT: [4] - AscalonFXA:1
+# CHECK-NEXT: [5] - AscalonFXB:1
+# CHECK-NEXT: [6] - AscalonFXC:2
+# CHECK-NEXT: [7] - AscalonFXD:2
+# CHECK-NEXT: [8] - AscalonLS:3
+# CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB
+# CHECK-NEXT: [10] - AscalonVA:1
+# CHECK-NEXT: [11] - AscalonVB:1
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -45,26 +49,29 @@ vslideup.vx v5, v7, x6, v0.t
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 4 1.00 vslidedown.vx v5, v7, t1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vslidedown.vx v5, v7, t1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 4 4.00 vslidedown.vx v5, v7, t1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 4 1.00 vslideup.vx v5, v7, t1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vslideup.vx v5, v7, t1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 4 4.00 vslideup.vx v5, v7, t1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 4 1.00 vslideup.vx v5, v7, t1, v0.t
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vslideup.vx v5, v7, t1, v0.t
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 4 4.00 vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 AscalonFX,AscalonV[1,3] VSLIDEDOWN_VX vslidedown.vx v5, v7, t1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[1,5] VSLIDEDOWN_VX vslidedown.vx v5, v7, t1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 AscalonFX,AscalonV[1,9] VSLIDEDOWN_VX vslidedown.vx v5, v7, t1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 AscalonFX,AscalonV[1,3] VSLIDEUP_VX vslideup.vx v5, v7, t1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[1,5] VSLIDEUP_VX vslideup.vx v5, v7, t1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 AscalonFX,AscalonV[1,9] VSLIDEUP_VX vslideup.vx v5, v7, t1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 1.00 4 AscalonFX,AscalonV[1,3] VSLIDEUP_VX vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[1,5] VSLIDEUP_VX vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 4.00 4 AscalonFX,AscalonV[1,9] VSLIDEUP_VX vslideup.vx v5, v7, t1, v0.t
# CHECK: Resources:
# CHECK-NEXT: [0] - AscalonFPA
@@ -83,25 +90,25 @@ vslideup.vx v5, v7, x6, v0.t
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
-# CHECK-NEXT: - - - - - - 4.00 5.00 - - - 27.00 33.00
+# CHECK-NEXT: - - 1.50 1.50 1.50 1.50 1.50 1.50 - - - 30.00 30.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 3.00 vslidedown.vx v5, v7, t1
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - 5.00 - vslidedown.vx v5, v7, t1
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 9.00 vslidedown.vx v5, v7, t1
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - 3.00 - vslideup.vx v5, v7, t1
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 5.00 - vslideup.vx v5, v7, t1
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 9.00 vslideup.vx v5, v7, t1
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 3.00 - vslideup.vx v5, v7, t1, v0.t
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - 5.00 - vslideup.vx v5, v7, t1, v0.t
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 9.00 vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.50 1.50 vslidedown.vx v5, v7, t1
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.50 2.50 vslidedown.vx v5, v7, t1
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.50 4.50 vslidedown.vx v5, v7, t1
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.50 1.50 vslideup.vx v5, v7, t1
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.50 2.50 vslideup.vx v5, v7, t1
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.50 4.50 vslideup.vx v5, v7, t1
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.50 1.50 vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.50 2.50 vslideup.vx v5, v7, t1, v0.t
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.50 4.50 vslideup.vx v5, v7, t1, v0.t
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
index 479aacc1a6e9d..807b9f94d2f02 100644
--- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vle-vse-vlm.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s
vsetvli zero, zero, e8, mf8, ta, ma
vle8.v v8, (a0)
@@ -179,15 +179,19 @@ vle64ff.v v8, (a0)
vsetvli zero, zero, e64, m8, ta, ma
vle64ff.v v8, (a0)
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 160
-# CHECK-NEXT: Total Cycles: 52
-# CHECK-NEXT: Total uOps: 160
-
-# CHECK: Dispatch Width: 8
-# CHECK-NEXT: uOps Per Cycle: 3.08
-# CHECK-NEXT: IPC: 3.08
-# CHECK-NEXT: Block RThroughput: 40.0
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB
+# CHECK-NEXT: [1] - AscalonFPA:1
+# CHECK-NEXT: [2] - AscalonFPB:1
+# CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD
+# CHECK-NEXT: [4] - AscalonFXA:1
+# CHECK-NEXT: [5] - AscalonFXB:1
+# CHECK-NEXT: [6] - AscalonFXC:2
+# CHECK-NEXT: [7] - AscalonFXD:2
+# CHECK-NEXT: [8] - AscalonLS:3
+# CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB
+# CHECK-NEXT: [10] - AscalonVA:1
+# CHECK-NEXT: [11] - AscalonVB:1
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -196,168 +200,171 @@ vle64ff.v v8, (a0)
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vle8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vle16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vle32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vle64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vle64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vle64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vse64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vlm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vsm.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vle8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vle16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vle32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 1 0.33 * vle64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vle64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vle64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vle64ff.v v8, (a0)
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLE8_V vle8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLE16_V vle16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLE32_V vle32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLE64_V vle64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE8_V vse8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE16_V vse16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE32_V vse32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSE64_V vse64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLM_V vlm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VSM_V vsm.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLE8FF_V vle8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLE16FF_V vle16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLE32FF_V vle32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLE64FF_V vle64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLE64FF_V vle64ff.v v8, (a0)
# CHECK: Resources:
# CHECK-NEXT: [0] - AscalonFPA
@@ -376,167 +383,167 @@ vle64ff.v v8, (a0)
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
-# CHECK-NEXT: - - - - - - - - 26.00 27.00 27.00 40.00 40.00
+# CHECK-NEXT: - - - - - - - - 26.67 26.67 26.67 40.00 40.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vle16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vle16.v v8, (a0)
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+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vse32.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vse64.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vse64.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vse64.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vse64.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsm.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle8ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle16ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle32ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle64ff.v v8, (a0)
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vle64ff.v v8, (a0)
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
index e6f6313531b7a..96cec1327621b 100644
--- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlse-vsse.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s
vsetvli zero, zero, e8, mf8, ta, ma
vlse8.v v8, (a0), t0
@@ -97,15 +97,19 @@ vsse64.v v8, (a0), t0
vsetvli zero, zero, e64, m8, ta, ma
vsse64.v v8, (a0), t0
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 88
-# CHECK-NEXT: Total Cycles: 53
-# CHECK-NEXT: Total uOps: 88
-
-# CHECK: Dispatch Width: 8
-# CHECK-NEXT: uOps Per Cycle: 1.66
-# CHECK-NEXT: IPC: 1.66
-# CHECK-NEXT: Block RThroughput: 22.0
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB
+# CHECK-NEXT: [1] - AscalonFPA:1
+# CHECK-NEXT: [2] - AscalonFPB:1
+# CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD
+# CHECK-NEXT: [4] - AscalonFXA:1
+# CHECK-NEXT: [5] - AscalonFXB:1
+# CHECK-NEXT: [6] - AscalonFXC:2
+# CHECK-NEXT: [7] - AscalonFXD:2
+# CHECK-NEXT: [8] - AscalonLS:3
+# CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB
+# CHECK-NEXT: [10] - AscalonVA:1
+# CHECK-NEXT: [11] - AscalonVB:1
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -114,96 +118,99 @@ vsse64.v v8, (a0), t0
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vlse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vlse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vlse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vlse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vlse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vlse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vlse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vsse8.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vsse16.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vsse32.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vsse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vsse64.v v8, (a0), t0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vsse64.v v8, (a0), t0
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSE8_V vlse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSE16_V vlse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSE32_V vlse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSE64_V vlse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSE8_V vsse8.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSE16_V vsse16.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSE32_V vsse32.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSE64_V vsse64.v v8, (a0), t0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSE64_V vsse64.v v8, (a0), t0
# CHECK: Resources:
# CHECK-NEXT: [0] - AscalonFPA
@@ -222,95 +229,95 @@ vsse64.v v8, (a0), t0
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
-# CHECK-NEXT: - - - - - - - - 14.00 15.00 15.00 22.00 22.00
+# CHECK-NEXT: - - - - - - - - 14.67 14.67 14.67 22.00 22.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse8.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse16.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse32.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vsse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vsse64.v v8, (a0), t0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vlse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse8.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse16.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse32.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse64.v v8, (a0), t0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsse64.v v8, (a0), t0
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
index 6f2070cd75ced..c528f647b4bfd 100644
--- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlseg-vsseg.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s
vsetvli zero, zero, e8, mf8, tu, mu
vlseg2e8.v v8,(a0)
@@ -1604,15 +1604,19 @@ vsoxseg8ei32.v v8, (a0), v16
vsetvli zero, zero, e64, m1, tu, mu
vsoxseg8ei64.v v8, (a0), v16
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 1540
-# CHECK-NEXT: Total Cycles: 631
-# CHECK-NEXT: Total uOps: 1540
-
-# CHECK: Dispatch Width: 8
-# CHECK-NEXT: uOps Per Cycle: 2.44
-# CHECK-NEXT: IPC: 2.44
-# CHECK-NEXT: Block RThroughput: 385.0
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB
+# CHECK-NEXT: [1] - AscalonFPA:1
+# CHECK-NEXT: [2] - AscalonFPB:1
+# CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD
+# CHECK-NEXT: [4] - AscalonFXA:1
+# CHECK-NEXT: [5] - AscalonFXB:1
+# CHECK-NEXT: [6] - AscalonFXC:2
+# CHECK-NEXT: [7] - AscalonFXD:2
+# CHECK-NEXT: [8] - AscalonLS:3
+# CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB
+# CHECK-NEXT: [10] - AscalonVA:1
+# CHECK-NEXT: [11] - AscalonVB:1
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -1621,1548 +1625,1551 @@ vsoxseg8ei64.v v8, (a0), v16
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg3e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg4e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 1 0.67 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 1 1.33 * vsseg2e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 1 0.67 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 1 1.33 * vsseg2e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 1 0.67 * vsseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 1 1.33 * vsseg2e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 1 0.67 * vsseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 1 1.33 * vsseg2e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 1 0.67 * vsseg3e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 1 0.67 * vsseg3e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 1 0.67 * vsseg3e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg3e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 1 0.67 * vsseg3e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 1 0.67 * vsseg4e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 1 0.67 * vsseg4e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 1 0.67 * vsseg4e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg4e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 1 0.67 * vsseg4e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg5e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg5e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg5e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg5e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg5e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg6e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg6e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg6e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg6e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg6e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg7e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg7e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg7e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg7e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg7e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg8e8.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg8e16.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg8e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg8e32.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vsseg8e64.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 128 0.33 * vlsseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vlsseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vlsseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vlsseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vlsseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vlsseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg3e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg3e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vlsseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vlsseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg4e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg4e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vlsseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg5e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg5e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg5e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vlsseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg6e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg6e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg6e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vlsseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg7e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg7e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg7e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vlsseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vlsseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlsseg8e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg8e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vlsseg8e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 128 0.33 * vssseg2e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vssseg2e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vssseg2e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vssseg2e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vssseg3e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vssseg3e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg3e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg3e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg3e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vssseg4e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vssseg4e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg4e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg4e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg4e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vssseg5e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg5e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg5e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg5e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg5e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vssseg6e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg6e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg6e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg6e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg6e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vssseg7e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg7e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg7e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg7e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg7e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vssseg8e8.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vssseg8e16.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vssseg8e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg8e32.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vssseg8e64.v v8, (a0), a1
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlseg2e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlseg2e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg2e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlseg2e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg2e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg2e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vlseg2e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg3e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg3e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg3e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg3e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg3e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg4e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg4e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg4e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg4e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 0.33 * vlseg4e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg5e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg6e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg7e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e8ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e16ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e32ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.33 * vlseg8e64ff.v v8, (a0)
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 128 0.33 * vluxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vluxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vluxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vluxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vluxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vluxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vluxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vluxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vluxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vluxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vluxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vluxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vluxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vluxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vluxseg8ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 128 0.33 * vloxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vloxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vloxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vloxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vloxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vloxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vloxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vloxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vloxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vloxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vloxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vloxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vloxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vloxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vloxseg8ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vsuxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsuxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vsuxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsuxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vsuxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsuxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsuxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsuxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsuxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsuxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsuxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsuxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsuxseg8ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 128 0.33 * vsoxseg2ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vsoxseg2ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsoxseg2ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsoxseg2ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vsoxseg3ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsoxseg3ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg3ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg3ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 64 0.33 * vsoxseg4ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsoxseg4ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg4ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg4ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsoxseg5ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg5ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg5ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg5ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsoxseg6ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg6ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg6ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg6ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsoxseg7ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg7ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg7ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg7ei64.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 32 0.33 * vsoxseg8ei8.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 16 0.33 * vsoxseg8ei16.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 0.33 * vsoxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg8ei32.v v8, (a0), v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 0.33 * vsoxseg8ei64.v v8, (a0), v16
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSEG2E8_V vlseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSEG2E16_V vlseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSEG2E32_V vlseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSEG2E64_V vlseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG3E8_V vlseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG3E16_V vlseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG3E32_V vlseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG3E64_V vlseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG4E8_V vlseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG4E16_V vlseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG4E32_V vlseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG4E64_V vlseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E8_V vlseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E16_V vlseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E32_V vlseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E64_V vlseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E8_V vlseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E16_V vlseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E32_V vlseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E64_V vlseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E8_V vlseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E16_V vlseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E32_V vlseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E64_V vlseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E8_V vlseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E16_V vlseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E32_V vlseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E64_V vlseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * 1 AscalonLS[1,3] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 1.33 * 1 AscalonLS[1,5] VSSEG2E8_V vsseg2e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * 1 AscalonLS[1,3] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 1.33 * 1 AscalonLS[1,5] VSSEG2E16_V vsseg2e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * 1 AscalonLS[1,3] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 1.33 * 1 AscalonLS[1,5] VSSEG2E32_V vsseg2e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * 1 AscalonLS[1,3] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 1.33 * 1 AscalonLS[1,5] VSSEG2E64_V vsseg2e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * 1 AscalonLS[1,3] VSSEG3E8_V vsseg3e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * 1 AscalonLS[1,3] VSSEG3E16_V vsseg3e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * 1 AscalonLS[1,3] VSSEG3E32_V vsseg3e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * 1 AscalonLS[1,3] VSSEG3E64_V vsseg3e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * 1 AscalonLS[1,3] VSSEG4E8_V vsseg4e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * 1 AscalonLS[1,3] VSSEG4E16_V vsseg4e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * 1 AscalonLS[1,3] VSSEG4E32_V vsseg4e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 0.67 * 1 AscalonLS[1,3] VSSEG4E64_V vsseg4e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG5E8_V vsseg5e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG5E16_V vsseg5e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG5E32_V vsseg5e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG5E64_V vsseg5e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG6E8_V vsseg6e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG6E16_V vsseg6e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG6E32_V vsseg6e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG6E64_V vsseg6e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG7E8_V vsseg7e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG7E16_V vsseg7e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG7E32_V vsseg7e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG7E64_V vsseg7e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG8E8_V vsseg8e8.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG8E16_V vsseg8e16.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG8E32_V vsseg8e32.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS[1,2] VSSEG8E64_V vsseg8e64.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 128 0.33 * 128 AscalonLS VLSSEG2E8_V vlsseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VLSSEG2E16_V vlsseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLSSEG2E32_V vlsseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLSSEG2E64_V vlsseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VLSSEG3E8_V vlsseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLSSEG3E16_V vlsseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG3E32_V vlsseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG3E64_V vlsseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VLSSEG4E8_V vlsseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLSSEG4E16_V vlsseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG4E32_V vlsseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG4E64_V vlsseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLSSEG5E8_V vlsseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG5E16_V vlsseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG5E32_V vlsseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG5E64_V vlsseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLSSEG6E8_V vlsseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG6E16_V vlsseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG6E32_V vlsseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG6E64_V vlsseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLSSEG7E8_V vlsseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG7E16_V vlsseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG7E32_V vlsseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG7E64_V vlsseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLSSEG8E8_V vlsseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLSSEG8E16_V vlsseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG8E32_V vlsseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLSSEG8E64_V vlsseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 128 0.33 * 128 AscalonLS VSSSEG2E8_V vssseg2e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VSSSEG2E16_V vssseg2e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSSSEG2E32_V vssseg2e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSSSEG2E64_V vssseg2e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VSSSEG3E8_V vssseg3e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSSSEG3E16_V vssseg3e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG3E32_V vssseg3e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG3E64_V vssseg3e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VSSSEG4E8_V vssseg4e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSSSEG4E16_V vssseg4e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG4E32_V vssseg4e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG4E64_V vssseg4e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSSSEG5E8_V vssseg5e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG5E16_V vssseg5e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG5E32_V vssseg5e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG5E64_V vssseg5e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSSSEG6E8_V vssseg6e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG6E16_V vssseg6e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG6E32_V vssseg6e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG6E64_V vssseg6e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSSSEG7E8_V vssseg7e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG7E16_V vssseg7e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG7E32_V vssseg7e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG7E64_V vssseg7e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSSSEG8E8_V vssseg8e8.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSSSEG8E16_V vssseg8e16.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG8E32_V vssseg8e32.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSSSEG8E64_V vssseg8e64.v v8, (a0), a1
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSEG2E8FF_V vlseg2e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSEG2E16FF_V vlseg2e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSEG2E32FF_V vlseg2e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLSEG2E64FF_V vlseg2e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG3E8FF_V vlseg3e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG3E16FF_V vlseg3e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG3E32FF_V vlseg3e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG3E64FF_V vlseg3e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG4E8FF_V vlseg4e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG4E16FF_V vlseg4e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG4E32FF_V vlseg4e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLSEG4E64FF_V vlseg4e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E8FF_V vlseg5e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E16FF_V vlseg5e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E32FF_V vlseg5e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG5E64FF_V vlseg5e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E8FF_V vlseg6e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E16FF_V vlseg6e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E32FF_V vlseg6e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG6E64FF_V vlseg6e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E8FF_V vlseg7e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E16FF_V vlseg7e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E32FF_V vlseg7e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG7E64FF_V vlseg7e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E8FF_V vlseg8e8ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E16FF_V vlseg8e16ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E32FF_V vlseg8e32ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.33 * 1 AscalonLS VLSEG8E64FF_V vlseg8e64ff.v v8, (a0)
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 128 0.33 * 128 AscalonLS VLUXSEG2EI8_V vluxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VLUXSEG2EI16_V vluxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLUXSEG2EI32_V vluxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLUXSEG2EI64_V vluxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VLUXSEG3EI8_V vluxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLUXSEG3EI16_V vluxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG3EI32_V vluxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG3EI64_V vluxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VLUXSEG4EI8_V vluxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLUXSEG4EI16_V vluxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG4EI32_V vluxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG4EI64_V vluxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLUXSEG5EI8_V vluxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG5EI16_V vluxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG5EI32_V vluxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG5EI64_V vluxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLUXSEG6EI8_V vluxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG6EI16_V vluxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG6EI32_V vluxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG6EI64_V vluxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLUXSEG7EI8_V vluxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG7EI16_V vluxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG7EI32_V vluxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG7EI64_V vluxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLUXSEG8EI8_V vluxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXSEG8EI16_V vluxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG8EI32_V vluxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXSEG8EI64_V vluxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 128 0.33 * 128 AscalonLS VLOXSEG2EI8_V vloxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VLOXSEG2EI16_V vloxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLOXSEG2EI32_V vloxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLOXSEG2EI64_V vloxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VLOXSEG3EI8_V vloxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLOXSEG3EI16_V vloxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG3EI32_V vloxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG3EI64_V vloxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VLOXSEG4EI8_V vloxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLOXSEG4EI16_V vloxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG4EI32_V vloxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG4EI64_V vloxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLOXSEG5EI8_V vloxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG5EI16_V vloxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG5EI32_V vloxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG5EI64_V vloxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLOXSEG6EI8_V vloxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG6EI16_V vloxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG6EI32_V vloxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG6EI64_V vloxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLOXSEG7EI8_V vloxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG7EI16_V vloxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG7EI32_V vloxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG7EI64_V vloxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VLOXSEG8EI8_V vloxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXSEG8EI16_V vloxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG8EI32_V vloxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXSEG8EI64_V vloxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VSUXSEG2EI8_V vsuxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSUXSEG2EI16_V vsuxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG2EI32_V vsuxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG2EI64_V vsuxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VSUXSEG3EI8_V vsuxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSUXSEG3EI16_V vsuxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG3EI32_V vsuxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG3EI64_V vsuxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VSUXSEG4EI8_V vsuxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSUXSEG4EI16_V vsuxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG4EI32_V vsuxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG4EI64_V vsuxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSUXSEG5EI8_V vsuxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG5EI16_V vsuxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG5EI32_V vsuxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG5EI64_V vsuxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSUXSEG6EI8_V vsuxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG6EI16_V vsuxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG6EI32_V vsuxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG6EI64_V vsuxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSUXSEG7EI8_V vsuxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG7EI16_V vsuxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG7EI32_V vsuxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG7EI64_V vsuxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSUXSEG8EI8_V vsuxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXSEG8EI16_V vsuxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG8EI32_V vsuxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXSEG8EI64_V vsuxseg8ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 128 0.33 * 128 AscalonLS VSOXSEG2EI8_V vsoxseg2ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VSOXSEG2EI16_V vsoxseg2ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSOXSEG2EI32_V vsoxseg2ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSOXSEG2EI64_V vsoxseg2ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VSOXSEG3EI8_V vsoxseg3ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSOXSEG3EI16_V vsoxseg3ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG3EI32_V vsoxseg3ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG3EI64_V vsoxseg3ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 64 0.33 * 64 AscalonLS VSOXSEG4EI8_V vsoxseg4ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSOXSEG4EI16_V vsoxseg4ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG4EI32_V vsoxseg4ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG4EI64_V vsoxseg4ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSOXSEG5EI8_V vsoxseg5ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG5EI16_V vsoxseg5ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG5EI32_V vsoxseg5ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG5EI64_V vsoxseg5ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSOXSEG6EI8_V vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG6EI16_V vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG6EI32_V vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG6EI64_V vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSOXSEG7EI8_V vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG7EI16_V vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG7EI32_V vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG7EI64_V vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 32 0.33 * 32 AscalonLS VSOXSEG8EI8_V vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXSEG8EI16_V vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG8EI32_V vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXSEG8EI64_V vsoxseg8ei64.v v8, (a0), v16
# CHECK: Resources:
# CHECK-NEXT: [0] - AscalonFPA
@@ -3181,1547 +3188,1547 @@ vsoxseg8ei64.v v8, (a0), v16
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
-# CHECK-NEXT: - - - - - - - - 293.00 293.00 294.00 385.00 385.00
+# CHECK-NEXT: - - - - - - - - 293.33 293.33 293.33 385.00 385.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg2e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg2e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg2e32.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg2e32.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg2e32.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg2e32.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg2e64.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg2e64.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg2e64.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg3e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg3e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg3e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg3e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg3e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg3e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg3e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg3e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg3e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg3e32.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg3e32.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg3e32.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg3e64.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg3e64.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg4e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg4e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg4e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg4e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg4e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg4e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg4e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg4e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg4e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg4e32.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg4e32.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg4e32.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg4e64.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg4e64.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg5e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg5e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg5e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg5e8.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - 1.00 - - - - vlseg5e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - 1.00 - - vlseg5e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - 1.00 - - - vlseg5e16.v v8, (a0)
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf2, tu, mu
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+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg6ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg6ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg6ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg6ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg7ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg7ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg7ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg7ei64.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg8ei8.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg8ei16.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg8ei32.v v8, (a0), v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxseg8ei64.v v8, (a0), v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
index db3cb1492cebe..cf5f8b04374be 100644
--- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vlxe-vsxe.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s
vsetvli zero, zero, e8, mf8, ta, ma
vluxei8.v v8, (a0), v0
@@ -193,15 +193,19 @@ vsoxei64.v v8, (a0), v0
vsetvli zero, zero, e64, m8, ta, ma
vsoxei64.v v8, (a0), v0
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 176
-# CHECK-NEXT: Total Cycles: 72
-# CHECK-NEXT: Total uOps: 176
-
-# CHECK: Dispatch Width: 8
-# CHECK-NEXT: uOps Per Cycle: 2.44
-# CHECK-NEXT: IPC: 2.44
-# CHECK-NEXT: Block RThroughput: 44.0
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB
+# CHECK-NEXT: [1] - AscalonFPA:1
+# CHECK-NEXT: [2] - AscalonFPB:1
+# CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD
+# CHECK-NEXT: [4] - AscalonFXA:1
+# CHECK-NEXT: [5] - AscalonFXB:1
+# CHECK-NEXT: [6] - AscalonFXC:2
+# CHECK-NEXT: [7] - AscalonFXD:2
+# CHECK-NEXT: [8] - AscalonLS:3
+# CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB
+# CHECK-NEXT: [10] - AscalonVA:1
+# CHECK-NEXT: [11] - AscalonVB:1
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -210,184 +214,187 @@ vsoxei64.v v8, (a0), v0
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vluxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vluxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vluxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vluxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vluxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vluxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vluxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vloxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vloxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vloxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vloxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vloxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vloxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vloxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vsuxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vsuxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vsuxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vsuxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vsoxei8.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vsoxei16.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vsoxei32.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, ta, ma
-# CHECK-NEXT: 1 2 0.33 * vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, ta, ma
-# CHECK-NEXT: 1 4 0.33 * vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, ta, ma
-# CHECK-NEXT: 1 8 0.33 * vsoxei64.v v8, (a0), v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, ta, ma
-# CHECK-NEXT: 1 16 0.33 * vsoxei64.v v8, (a0), v0
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXEI8_V vluxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXEI16_V vluxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXEI32_V vluxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLUXEI64_V vluxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXEI8_V vloxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXEI16_V vloxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXEI32_V vloxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VLOXEI64_V vloxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXEI8_V vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXEI16_V vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXEI32_V vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSUXEI64_V vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXEI8_V vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXEI16_V vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXEI32_V vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: 1 2 0.33 * 2 AscalonLS VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: 1 4 0.33 * 4 AscalonLS VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: 1 8 0.33 * 8 AscalonLS VSOXEI64_V vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: 1 16 0.33 * 16 AscalonLS VSOXEI64_V vsoxei64.v v8, (a0), v0
# CHECK: Resources:
# CHECK-NEXT: [0] - AscalonFPA
@@ -406,183 +413,183 @@ vsoxei64.v v8, (a0), v0
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
-# CHECK-NEXT: - - - - - - - - 29.00 29.00 30.00 44.00 44.00
+# CHECK-NEXT: - - - - - - - - 29.33 29.33 29.33 44.00 44.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vluxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vluxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vluxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vloxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsuxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei8.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei16.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei32.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei64.v v8, (a0), v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, ta, ma
+# CHECK-NEXT: - - - - - - - - 0.33 0.33 0.33 - - vsoxei64.v v8, (a0), v0
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
index 566179e435680..c131414bc78e5 100644
--- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vmv.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s
vsetvli zero, zero, e8, mf8, tu, mu
vmv1r.v v8, v16
@@ -290,15 +290,19 @@ vsetvli zero, zero, e64, m8, tu, mu
vfmv.s.f v8, f5
vfmv.f.s f7, v16
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 280
-# CHECK-NEXT: Total Cycles: 327
-# CHECK-NEXT: Total uOps: 280
-
-# CHECK: Dispatch Width: 8
-# CHECK-NEXT: uOps Per Cycle: 0.86
-# CHECK-NEXT: IPC: 0.86
-# CHECK-NEXT: Block RThroughput: 324.0
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB
+# CHECK-NEXT: [1] - AscalonFPA:1
+# CHECK-NEXT: [2] - AscalonFPB:1
+# CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD
+# CHECK-NEXT: [4] - AscalonFXA:1
+# CHECK-NEXT: [5] - AscalonFXB:1
+# CHECK-NEXT: [6] - AscalonFXC:2
+# CHECK-NEXT: [7] - AscalonFXD:2
+# CHECK-NEXT: [8] - AscalonLS:3
+# CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB
+# CHECK-NEXT: [10] - AscalonVA:1
+# CHECK-NEXT: [11] - AscalonVB:1
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -307,288 +311,291 @@ vfmv.f.s f7, v16
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 1 0.50 vmv1r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv2r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 4 2.00 vmv4r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vmv8r.v v8, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv.s.x v8, t0
-# CHECK-NEXT: 1 2 1.00 vmv.x.s t2, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv.s.x v8, t0
-# CHECK-NEXT: 1 2 1.00 vmv.x.s t2, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv.s.x v8, t0
-# CHECK-NEXT: 1 2 1.00 vmv.x.s t2, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vmv.s.x v8, t0
-# CHECK-NEXT: 1 2 1.00 vmv.x.s t2, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 2 1.00 vfmv.s.f v8, ft5
-# CHECK-NEXT: 1 2 1.00 vfmv.f.s ft7, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vfmv.s.f v8, ft5
-# CHECK-NEXT: 1 2 1.00 vfmv.f.s ft7, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 2 1.00 vfmv.s.f v8, ft5
-# CHECK-NEXT: 1 2 1.00 vfmv.f.s ft7, v16
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 2 1.00 vfmv.s.f v8, ft5
-# CHECK-NEXT: 1 2 1.00 vfmv.f.s ft7, v16
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonV VMV1R_V vmv1r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonV[2] VMV2R_V vmv2r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonV[4] VMV4R_V vmv4r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonV[8] VMV8R_V vmv8r.v v8, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VMV_S_X vmv.s.x v8, t0
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VMV_X_S vmv.x.s t2, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VMV_S_X vmv.s.x v8, t0
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VMV_X_S vmv.x.s t2, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VMV_S_X vmv.s.x v8, t0
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VMV_X_S vmv.x.s t2, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VMV_S_X vmv.s.x v8, t0
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VMV_X_S vmv.x.s t2, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFMV_S_F vfmv.s.f v8, ft5
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFMV_F_S vfmv.f.s ft7, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFMV_S_F vfmv.s.f v8, ft5
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFMV_F_S vfmv.f.s ft7, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFMV_S_F vfmv.s.f v8, ft5
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFMV_F_S vfmv.f.s ft7, v16
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFMV_S_F vfmv.s.f v8, ft5
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFMV_F_S vfmv.f.s ft7, v16
# CHECK: Resources:
# CHECK-NEXT: [0] - AscalonFPA
@@ -607,287 +614,287 @@ vfmv.f.s f7, v16
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
-# CHECK-NEXT: - - 2.00 2.00 4.00 4.00 2.00 2.00 - - - 324.00 324.00
+# CHECK-NEXT: - - 2.67 2.67 2.67 2.67 2.67 2.67 - - - 324.00 324.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vmv1r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 2.00 vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 2.00 - vmv2r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e8, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e8, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, mf2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, mf8, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - - 4.00 vmv4r.v v8, v16
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf4, tu, mu
-# CHECK-NEXT: - - - - - - - - - - - 4.00 - vmv4r.v v8, v16
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+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 1.00 1.00 vmv2r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 2.00 2.00 vmv4r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e8, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, mf2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - - - - - - - - - - 4.00 4.00 vmv8r.v v8, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vmv.s.x v8, t0
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vmv.x.s t2, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vmv.s.x v8, t0
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vmv.x.s t2, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vmv.s.x v8, t0
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vmv.x.s t2, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vmv.s.x v8, t0
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vmv.x.s t2, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfmv.s.f v8, ft5
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfmv.f.s ft7, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfmv.s.f v8, ft5
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfmv.f.s ft7, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfmv.s.f v8, ft5
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfmv.f.s ft7, v16
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfmv.s.f v8, ft5
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfmv.f.s ft7, v16
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
index 558e6ac267965..020a0a0192aa4 100644
--- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vreduce.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s
# Simple integer reductions: varies by LMUL
vsetvli zero, zero, e32, m1, tu, mu
@@ -161,15 +161,19 @@ vsetvli zero, zero, e64, m8, tu, mu
vfredmin.vs v5, v7, v8
vfredmax.vs v5, v7, v8
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 116
-# CHECK-NEXT: Total Cycles: 563
-# CHECK-NEXT: Total uOps: 116
-
-# CHECK: Dispatch Width: 8
-# CHECK-NEXT: uOps Per Cycle: 0.21
-# CHECK-NEXT: IPC: 0.21
-# CHECK-NEXT: Block RThroughput: 545.0
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB
+# CHECK-NEXT: [1] - AscalonFPA:1
+# CHECK-NEXT: [2] - AscalonFPB:1
+# CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD
+# CHECK-NEXT: [4] - AscalonFXA:1
+# CHECK-NEXT: [5] - AscalonFXB:1
+# CHECK-NEXT: [6] - AscalonFXC:2
+# CHECK-NEXT: [7] - AscalonFXD:2
+# CHECK-NEXT: [8] - AscalonLS:3
+# CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB
+# CHECK-NEXT: [10] - AscalonVA:1
+# CHECK-NEXT: [11] - AscalonVB:1
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -178,124 +182,127 @@ vfredmax.vs v5, v7, v8
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vredsum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vredsum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vredsum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vredsum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 2 1.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 4 2.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 8 4.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 2 1.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 4 2.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 8 4.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 2 1.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 4 2.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 8 4.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 18 9.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 36 18.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 72 36.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 144 72.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 18 9.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 36 18.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 72 36.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 144 72.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 18 9.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 36 18.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 72 36.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: 1 144 72.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 2 1.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 4 2.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 8 4.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 2 1.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 4 2.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 8 4.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: 1 1 0.50 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: 1 2 1.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 2 1.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: 1 4 2.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 4 2.00 vfredmax.vs v5, v7, v8
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: 1 8 4.00 vfredmin.vs v5, v7, v8
-# CHECK-NEXT: 1 8 4.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VREDSUM_VS vredsum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VREDSUM_VS vredsum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VREDSUM_VS vredsum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VREDSUM_VS vredsum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VREDMIN_VS vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VREDMAX_VS vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VREDMIN_VS vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VREDMAX_VS vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VREDMIN_VS vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VREDMAX_VS vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VREDMIN_VS vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VREDMAX_VS vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VREDMIN_VS vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VREDMAX_VS vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VREDMIN_VS vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VREDMAX_VS vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VREDMIN_VS vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VREDMAX_VS vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VREDMIN_VS vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VREDMAX_VS vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VREDMIN_VS vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VREDMAX_VS vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VREDMIN_VS vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VREDMAX_VS vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VREDMIN_VS vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VREDMAX_VS vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VREDMIN_VS vredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VREDMAX_VS vredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VFREDUSUM_VS vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 18 9.00 18 AscalonFX,AscalonV[18] VFREDOSUM_VS vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFREDUSUM_VS vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 36 18.00 36 AscalonFX,AscalonV[36] VFREDOSUM_VS vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VFREDUSUM_VS vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 72 36.00 72 AscalonFX,AscalonV[72] VFREDOSUM_VS vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VFREDUSUM_VS vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 144 72.00 144 AscalonFX,AscalonV[144] VFREDOSUM_VS vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VFREDUSUM_VS vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 18 9.00 18 AscalonFX,AscalonV[18] VFREDOSUM_VS vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFREDUSUM_VS vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 36 18.00 36 AscalonFX,AscalonV[36] VFREDOSUM_VS vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VFREDUSUM_VS vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 72 36.00 72 AscalonFX,AscalonV[72] VFREDOSUM_VS vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VFREDUSUM_VS vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 144 72.00 144 AscalonFX,AscalonV[144] VFREDOSUM_VS vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VFREDUSUM_VS vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 18 9.00 18 AscalonFX,AscalonV[18] VFREDOSUM_VS vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFREDUSUM_VS vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 36 18.00 36 AscalonFX,AscalonV[36] VFREDOSUM_VS vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VFREDUSUM_VS vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 72 36.00 72 AscalonFX,AscalonV[72] VFREDOSUM_VS vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VFREDUSUM_VS vfredusum.vs v5, v7, v8
+# CHECK-NEXT: 1 144 72.00 144 AscalonFX,AscalonV[144] VFREDOSUM_VS vfredosum.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VFREDMIN_VS vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VFREDMAX_VS vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFREDMIN_VS vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFREDMAX_VS vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VFREDMIN_VS vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VFREDMAX_VS vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VFREDMIN_VS vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VFREDMAX_VS vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VFREDMIN_VS vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VFREDMAX_VS vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFREDMIN_VS vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFREDMAX_VS vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VFREDMIN_VS vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VFREDMAX_VS vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VFREDMIN_VS vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VFREDMAX_VS vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VFREDMIN_VS vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VFREDMAX_VS vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFREDMIN_VS vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 2 1.00 2 AscalonFX,AscalonV[2] VFREDMAX_VS vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VFREDMIN_VS vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 4 2.00 4 AscalonFX,AscalonV[4] VFREDMAX_VS vfredmax.vs v5, v7, v8
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VFREDMIN_VS vfredmin.vs v5, v7, v8
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VFREDMAX_VS vfredmax.vs v5, v7, v8
# CHECK: Resources:
# CHECK-NEXT: [0] - AscalonFPA
@@ -314,123 +321,123 @@ vfredmax.vs v5, v7, v8
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
-# CHECK-NEXT: - - 3.00 3.00 30.00 30.00 5.00 5.00 - - - 530.00 560.00
+# CHECK-NEXT: - - 12.67 12.67 12.67 12.67 12.67 12.67 - - - 545.00 545.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 1.00 vredsum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 2.00 vredsum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 4.00 vredsum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - 1.00 - - - - 8.00 - vredsum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - - 1.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - 1.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - 2.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - 1.00 - - - - - - - - 4.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - 1.00 - - - - - - - - 4.00 - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 8.00 - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 8.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - - 1.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 1.00 - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - 2.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - 1.00 - - - - - - - - 4.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - 1.00 - - - - - - - - 4.00 - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 8.00 - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 8.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - - 1.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 1.00 - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - 2.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - 1.00 - - - - - - - - 4.00 vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - 1.00 - - - - - - - - 4.00 - vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - 8.00 - vredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 8.00 vredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - - 1.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 18.00 - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - - 2.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - 36.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 4.00 - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 72.00 - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - - 8.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - 144.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 18.00 - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 36.00 - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 4.00 - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 72.00 - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - - 8.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - 144.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 18.00 - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 36.00 - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 4.00 - vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 72.00 - vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - - 8.00 vfredusum.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - 144.00 vfredosum.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e16, m1, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 1.00 - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m2, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 2.00 - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m4, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 4.00 - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 4.00 - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e16, m8, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 8.00 - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 8.00 - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 1.00 - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 2.00 - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 4.00 - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 4.00 - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 8.00 - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 8.00 - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m1, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 1.00 - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m2, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 2.00 - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 2.00 - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m4, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 4.00 - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 4.00 - vfredmax.vs v5, v7, v8
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e64, m8, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 8.00 - vfredmin.vs v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 8.00 - vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vredsum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vredsum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vredsum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vredsum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 9.00 9.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 18.00 18.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 36.00 36.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 72.00 72.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 9.00 9.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 18.00 18.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 36.00 36.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 72.00 72.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 9.00 9.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 18.00 18.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 36.00 36.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vfredusum.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 72.00 72.00 vfredosum.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e16, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.00 1.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.00 2.00 vfredmax.vs v5, v7, v8
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e64, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vfredmin.vs v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vfredmax.vs v5, v7, v8
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
index f59b7aec7d043..9e2e0a5a2aa7a 100644
--- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vrgather-vcompress.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s
vsetvli zero, zero, e32, m1, tu, mu
vrgather.vv v5, v7, v8
@@ -17,15 +17,19 @@ vsetvli zero, zero, e32, m8, tu, mu
vrgather.vv v5, v7, v8
vcompress.vm v4, v9, v0
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 12
-# CHECK-NEXT: Total Cycles: 77
-# CHECK-NEXT: Total uOps: 12
-
-# CHECK: Dispatch Width: 8
-# CHECK-NEXT: uOps Per Cycle: 0.16
-# CHECK-NEXT: IPC: 0.16
-# CHECK-NEXT: Block RThroughput: 72.0
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB
+# CHECK-NEXT: [1] - AscalonFPA:1
+# CHECK-NEXT: [2] - AscalonFPB:1
+# CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD
+# CHECK-NEXT: [4] - AscalonFXA:1
+# CHECK-NEXT: [5] - AscalonFXB:1
+# CHECK-NEXT: [6] - AscalonFXC:2
+# CHECK-NEXT: [7] - AscalonFXD:2
+# CHECK-NEXT: [8] - AscalonLS:3
+# CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB
+# CHECK-NEXT: [10] - AscalonVA:1
+# CHECK-NEXT: [11] - AscalonVB:1
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -34,20 +38,23 @@ vcompress.vm v4, v9, v0
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: 1 5 1.50 vrgather.vv v5, v7, v8
-# CHECK-NEXT: 1 5 1.50 vcompress.vm v4, v9, v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: 1 7 2.50 vrgather.vv v5, v7, v8
-# CHECK-NEXT: 1 7 2.50 vcompress.vm v4, v9, v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: 1 15 6.50 vrgather.vv v5, v7, v8
-# CHECK-NEXT: 1 15 6.50 vcompress.vm v4, v9, v0
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: 1 51 24.50 vrgather.vv v5, v7, v8
-# CHECK-NEXT: 1 51 24.50 vcompress.vm v4, v9, v0
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: 1 5 1.50 5 AscalonFX,AscalonV[3] VRGATHER_VV vrgather.vv v5, v7, v8
+# CHECK-NEXT: 1 5 1.50 5 AscalonFX,AscalonV[3] VCOMPRESS_VM vcompress.vm v4, v9, v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: 1 7 2.50 7 AscalonFX,AscalonV[5] VRGATHER_VV vrgather.vv v5, v7, v8
+# CHECK-NEXT: 1 7 2.50 7 AscalonFX,AscalonV[5] VCOMPRESS_VM vcompress.vm v4, v9, v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: 1 15 6.50 15 AscalonFX,AscalonV[13] VRGATHER_VV vrgather.vv v5, v7, v8
+# CHECK-NEXT: 1 15 6.50 15 AscalonFX,AscalonV[13] VCOMPRESS_VM vcompress.vm v4, v9, v0
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: 1 51 24.50 51 AscalonFX,AscalonV[49] VRGATHER_VV vrgather.vv v5, v7, v8
+# CHECK-NEXT: 1 51 24.50 51 AscalonFX,AscalonV[49] VCOMPRESS_VM vcompress.vm v4, v9, v0
# CHECK: Resources:
# CHECK-NEXT: [0] - AscalonFPA
@@ -66,19 +73,19 @@ vcompress.vm v4, v9, v0
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
-# CHECK-NEXT: - - 1.00 1.00 2.00 2.00 1.00 1.00 - - - 72.00 72.00
+# CHECK-NEXT: - - 1.33 1.33 1.33 1.33 1.33 1.33 - - - 72.00 72.00
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, tu, mu
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 3.00 vrgather.vv v5, v7, v8
-# CHECK-NEXT: - - - - - - 1.00 - - - - 3.00 - vcompress.vm v4, v9, v0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m2, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - 5.00 - vrgather.vv v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - - 5.00 vcompress.vm v4, v9, v0
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m4, tu, mu
-# CHECK-NEXT: - - - - - 1.00 - - - - - - 13.00 vrgather.vv v5, v7, v8
-# CHECK-NEXT: - - - - 1.00 - - - - - - 13.00 - vcompress.vm v4, v9, v0
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, tu, mu
-# CHECK-NEXT: - - - 1.00 - - - - - - - - 49.00 vrgather.vv v5, v7, v8
-# CHECK-NEXT: - - 1.00 - - - - - - - - 49.00 - vcompress.vm v4, v9, v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.50 1.50 vrgather.vv v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 1.50 1.50 vcompress.vm v4, v9, v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m2, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.50 2.50 vrgather.vv v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 2.50 2.50 vcompress.vm v4, v9, v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m4, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 6.50 6.50 vrgather.vv v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 6.50 6.50 vcompress.vm v4, v9, v0
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, tu, mu
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 24.50 24.50 vrgather.vv v5, v7, v8
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 24.50 24.50 vcompress.vm v4, v9, v0
diff --git a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
index 095d03441fbb0..cbddf81d5867c 100644
--- a/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
+++ b/llvm/test/tools/llvm-mca/RISCV/tt-ascalon-d8/vshift-vmul.s
@@ -1,5 +1,5 @@
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
-# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -iterations=1 < %s | FileCheck %s
+# RUN: llvm-mca -mtriple=riscv64 -mcpu=tt-ascalon-d8 -instruction-tables=full -iterations=1 < %s | FileCheck %s
vsetvli zero, zero, e32, m1, ta, ma
@@ -37,15 +37,19 @@ vmul.vx v1, v2, t1
vmadd.vv v1, v2, v5
vmadd.vx v1, t1, v2
-# CHECK: Iterations: 1
-# CHECK-NEXT: Instructions: 25
-# CHECK-NEXT: Total Cycles: 38
-# CHECK-NEXT: Total uOps: 25
-
-# CHECK: Dispatch Width: 8
-# CHECK-NEXT: uOps Per Cycle: 0.66
-# CHECK-NEXT: IPC: 0.66
-# CHECK-NEXT: Block RThroughput: 26.5
+# CHECK: Resources:
+# CHECK-NEXT: [0] - AscalonFP:2 AscalonFPA, AscalonFPB
+# CHECK-NEXT: [1] - AscalonFPA:1
+# CHECK-NEXT: [2] - AscalonFPB:1
+# CHECK-NEXT: [3] - AscalonFX:6 AscalonFXA, AscalonFXB, AscalonFXC, AscalonFXC, AscalonFXD, AscalonFXD
+# CHECK-NEXT: [4] - AscalonFXA:1
+# CHECK-NEXT: [5] - AscalonFXB:1
+# CHECK-NEXT: [6] - AscalonFXC:2
+# CHECK-NEXT: [7] - AscalonFXD:2
+# CHECK-NEXT: [8] - AscalonLS:3
+# CHECK-NEXT: [9] - AscalonV:2 AscalonVA, AscalonVB
+# CHECK-NEXT: [10] - AscalonVA:1
+# CHECK-NEXT: [11] - AscalonVB:1
# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
@@ -54,33 +58,36 @@ vmadd.vx v1, t1, v2
# CHECK-NEXT: [4]: MayLoad
# CHECK-NEXT: [5]: MayStore
# CHECK-NEXT: [6]: HasSideEffects (U)
-
-# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: 1 1 0.50 vsll.vv v1, v2, v5
-# CHECK-NEXT: 1 1 0.50 vsll.vx v1, v2, t0
-# CHECK-NEXT: 1 1 0.50 vsll.vi v1, v2, 7
-# CHECK-NEXT: 1 1 0.50 vsrl.vv v1, v2, v5
-# CHECK-NEXT: 1 1 0.50 vsrl.vx v1, v2, t0
-# CHECK-NEXT: 1 1 0.50 vsrl.vi v1, v2, 7
-# CHECK-NEXT: 1 1 0.50 vsra.vv v1, v2, v5
-# CHECK-NEXT: 1 1 0.50 vsra.vx v1, v2, t0
-# CHECK-NEXT: 1 1 0.50 vsra.vi v1, v2, 7
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, mf4, ta, ma
-# CHECK-NEXT: 1 1 0.50 vsll.vv v1, v2, v5
-# CHECK-NEXT: 1 1 0.50 vsll.vx v1, v2, t0
-# CHECK-NEXT: 1 1 0.50 vsll.vi v1, v2, 7
-# CHECK-NEXT: 1 1 0.50 vsrl.vv v1, v2, v5
-# CHECK-NEXT: 1 1 0.50 vsrl.vx v1, v2, t0
-# CHECK-NEXT: 1 1 0.50 vsrl.vi v1, v2, 7
-# CHECK-NEXT: 1 1 0.50 vsra.vv v1, v2, v5
-# CHECK-NEXT: 1 1 0.50 vsra.vx v1, v2, t0
-# CHECK-NEXT: 1 1 0.50 vsra.vi v1, v2, 7
-# CHECK-NEXT: 1 1 0.50 U vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: 1 8 4.00 vmul.vv v1, v2, v5
-# CHECK-NEXT: 1 8 4.00 vmul.vx v1, v2, t1
-# CHECK-NEXT: 1 8 4.00 vmadd.vv v1, v2, v5
-# CHECK-NEXT: 1 8 4.00 vmadd.vx v1, t1, v2
+# CHECK-NEXT: [7]: Bypass Latency
+# CHECK-NEXT: [8]: Resources (<Name> | <Name>[<ReleaseAtCycle>] | <Name>[<AcquireAtCycle>,<ReleaseAtCycle])
+# CHECK-NEXT: [9]: LLVM Opcode Name
+
+# CHECK: [1] [2] [3] [4] [5] [6] [7] [8] [9] Instructions:
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSLL_VV vsll.vv v1, v2, v5
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSLL_VX vsll.vx v1, v2, t0
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSLL_VI vsll.vi v1, v2, 7
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSRL_VV vsrl.vv v1, v2, v5
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSRL_VX vsrl.vx v1, v2, t0
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSRL_VI vsrl.vi v1, v2, 7
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSRA_VV vsra.vv v1, v2, v5
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSRA_VX vsra.vx v1, v2, t0
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSRA_VI vsra.vi v1, v2, 7
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, mf4, ta, ma
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSLL_VV vsll.vv v1, v2, v5
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSLL_VX vsll.vx v1, v2, t0
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSLL_VI vsll.vi v1, v2, 7
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSRL_VV vsrl.vv v1, v2, v5
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSRL_VX vsrl.vx v1, v2, t0
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSRL_VI vsrl.vi v1, v2, 7
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSRA_VV vsra.vv v1, v2, v5
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSRA_VX vsra.vx v1, v2, t0
+# CHECK-NEXT: 1 1 0.50 1 AscalonFX,AscalonV VSRA_VI vsra.vi v1, v2, 7
+# CHECK-NEXT: 1 1 0.50 U 0 AscalonV VSETVLI vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VMUL_VV vmul.vv v1, v2, v5
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VMUL_VX vmul.vx v1, v2, t1
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VMADD_VV vmadd.vv v1, v2, v5
+# CHECK-NEXT: 1 8 4.00 8 AscalonFX,AscalonV[8] VMADD_VX vmadd.vx v1, t1, v2
# CHECK: Resources:
# CHECK-NEXT: [0] - AscalonFPA
@@ -99,32 +106,32 @@ vmadd.vx v1, t1, v2
# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8]
-# CHECK-NEXT: - - 3.00 3.00 3.00 3.00 5.00 5.00 - - - 26.00 27.00
+# CHECK-NEXT: - - 3.67 3.67 3.67 3.67 3.67 3.67 - - - 26.50 26.50
# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4.0] [4.1] [5.0] [5.1] [6.0] [6.1] [6.2] [7] [8] Instructions:
-# CHECK-NEXT: - - - - - - - - - - - - 1.00 vsetvli zero, zero, e32, m1, ta, ma
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 1.00 vsll.vv v1, v2, v5
-# CHECK-NEXT: - - - - - - 1.00 - - - - 1.00 - vsll.vx v1, v2, t0
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 1.00 vsll.vi v1, v2, 7
-# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vsrl.vv v1, v2, v5
-# CHECK-NEXT: - - - - 1.00 - - - - - - - 1.00 vsrl.vx v1, v2, t0
-# CHECK-NEXT: - - - 1.00 - - - - - - - 1.00 - vsrl.vi v1, v2, 7
-# CHECK-NEXT: - - 1.00 - - - - - - - - - 1.00 vsra.vv v1, v2, v5
-# CHECK-NEXT: - - - - - - 1.00 - - - - 1.00 - vsra.vx v1, v2, t0
-# CHECK-NEXT: - - - - - - - 1.00 - - - - 1.00 vsra.vi v1, v2, 7
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, mf4, ta, ma
-# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vsll.vv v1, v2, v5
-# CHECK-NEXT: - - - - 1.00 - - - - - - - 1.00 vsll.vx v1, v2, t0
-# CHECK-NEXT: - - - 1.00 - - - - - - - - 1.00 vsll.vi v1, v2, 7
-# CHECK-NEXT: - - 1.00 - - - - - - - - 1.00 - vsrl.vv v1, v2, v5
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 1.00 vsrl.vx v1, v2, t0
-# CHECK-NEXT: - - - - - - - 1.00 - - - 1.00 - vsrl.vi v1, v2, 7
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 1.00 vsra.vv v1, v2, v5
-# CHECK-NEXT: - - - - - 1.00 - - - - - 1.00 - vsra.vx v1, v2, t0
-# CHECK-NEXT: - - - - 1.00 - - - - - - - 1.00 vsra.vi v1, v2, 7
-# CHECK-NEXT: - - - - - - - - - - - 1.00 - vsetvli zero, zero, e32, m8, ta, ma
-# CHECK-NEXT: - - - 1.00 - - - - - - - 8.00 - vmul.vv v1, v2, v5
-# CHECK-NEXT: - - 1.00 - - - - - - - - - 8.00 vmul.vx v1, v2, t1
-# CHECK-NEXT: - - - - - - - 1.00 - - - 8.00 - vmadd.vv v1, v2, v5
-# CHECK-NEXT: - - - - - - 1.00 - - - - - 8.00 vmadd.vx v1, t1, v2
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m1, ta, ma
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsll.vv v1, v2, v5
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsll.vx v1, v2, t0
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsll.vi v1, v2, 7
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsrl.vv v1, v2, v5
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsrl.vx v1, v2, t0
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsrl.vi v1, v2, 7
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsra.vv v1, v2, v5
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsra.vx v1, v2, t0
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsra.vi v1, v2, 7
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, mf4, ta, ma
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsll.vv v1, v2, v5
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsll.vx v1, v2, t0
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsll.vi v1, v2, 7
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsrl.vv v1, v2, v5
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsrl.vx v1, v2, t0
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsrl.vi v1, v2, 7
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsra.vv v1, v2, v5
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsra.vx v1, v2, t0
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 0.50 0.50 vsra.vi v1, v2, 7
+# CHECK-NEXT: - - - - - - - - - - - 0.50 0.50 vsetvli zero, zero, e32, m8, ta, ma
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vmul.vv v1, v2, v5
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vmul.vx v1, v2, t1
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vmadd.vv v1, v2, v5
+# CHECK-NEXT: - - 0.17 0.17 0.17 0.17 0.17 0.17 - - - 4.00 4.00 vmadd.vx v1, t1, v2
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