[llvm] [RISCV] tt-ascalon-d8 vector scheduling (PR #167066)

[Petr Penzin via llvm-commits]

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@@ -633,6 +633,13 @@ def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
                                                   FeatureUnalignedVectorMem]),
                                                  [TuneNoDefaultUnroll,
                                                   TuneNLogNVRGather,
+                                                  TuneOptimizedNF2SegmentLoadStore,
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ppenzin wrote:

Can do either way, I did call them out in the description though. 

https://github.com/llvm/llvm-project/pull/167066