[llvm] 6886d49 - [RISCV] Add an option to enable CFIInstrInserter. (#164477)

[via llvm-commits]

Author: Mikhail Gudim
Date: 2025-11-18T02:46:43-05:00
New Revision: 6886d4945f8c46b64fecf2fa6708128bcee8cadc

URL: https://github.com/llvm/llvm-project/commit/6886d4945f8c46b64fecf2fa6708128bcee8cadc
DIFF: https://github.com/llvm/llvm-project/commit/6886d4945f8c46b64fecf2fa6708128bcee8cadc.diff

LOG: [RISCV] Add an option to enable CFIInstrInserter. (#164477)

Added: 
    llvm/test/CodeGen/RISCV/pipeline-options.ll

Modified: 
    llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
    llvm/lib/Target/RISCV/RISCVFrameLowering.h
    llvm/lib/Target/RISCV/RISCVTargetMachine.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index f7fc9528920a6..75e7cf347e461 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -2507,3 +2507,12 @@ void RISCVFrameLowering::inlineStackProbe(MachineFunction &MF,
     }
   }
 }
+
+int RISCVFrameLowering::getInitialCFAOffset(const MachineFunction &MF) const {
+  return 0;
+}
+
+Register
+RISCVFrameLowering::getInitialCFARegister(const MachineFunction &MF) const {
+  return RISCV::X2;
+}

diff  --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
index 6af63a4885f35..87980dfb09f96 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h
@@ -23,6 +23,9 @@ class RISCVFrameLowering : public TargetFrameLowering {
 public:
   explicit RISCVFrameLowering(const RISCVSubtarget &STI);
 
+  int getInitialCFAOffset(const MachineFunction &MF) const override;
+  Register getInitialCFARegister(const MachineFunction &MF) const override;
+
   void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
   void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
 

diff  --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 16ef67da83128..911bd7ee2876f 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -103,6 +103,11 @@ static cl::opt<bool>
                            cl::desc("Enable Machine Pipeliner for RISC-V"),
                            cl::init(false), cl::Hidden);
 
+static cl::opt<bool> EnableCFIInstrInserter(
+    "riscv-enable-cfi-instr-inserter",
+    cl::desc("Enable CFI Instruction Inserter for RISC-V"), cl::init(false),
+    cl::Hidden);
+
 extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
   RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
@@ -169,7 +174,7 @@ RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
   if (TT.isOSFuchsia() && !TT.isArch64Bit())
     report_fatal_error("Fuchsia is only supported for 64-bit");
 
-  setCFIFixup(true);
+  setCFIFixup(!EnableCFIInstrInserter);
 }
 
 const RISCVSubtarget *
@@ -578,6 +583,9 @@ void RISCVPassConfig::addPreEmitPass2() {
   addPass(createUnpackMachineBundles([&](const MachineFunction &MF) {
     return MF.getFunction().getParent()->getModuleFlag("kcfi");
   }));
+
+  if (EnableCFIInstrInserter)
+    addPass(createCFIInstrInserter());
 }
 
 void RISCVPassConfig::addMachineSSAOptimization() {

diff  --git a/llvm/test/CodeGen/RISCV/pipeline-options.ll b/llvm/test/CodeGen/RISCV/pipeline-options.ll
new file mode 100644
index 0000000000000..26c9aaba09c94
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/pipeline-options.ll
@@ -0,0 +1,35 @@
+; RUN: llc -mtriple=riscv64 -O3  \
+; RUN: -debug-pass=Structure < %s -o /dev/null 2>&1 | \
+; RUN:   FileCheck %s --check-prefix=O3-WITHOUT-ENABLE-CFI-INSTR-INSERTER
+
+; RUN: llc -mtriple=riscv64 -O3  \
+; RUN: --riscv-enable-cfi-instr-inserter=true \
+; RUN: -debug-pass=Structure < %s -o /dev/null 2>&1 | \
+; RUN:   FileCheck %s --check-prefix=O3-ENABLE-CFI-INSTR-INSERTER
+
+; RUN: llc -mtriple=riscv64 -O0  \
+; RUN: -debug-pass=Structure < %s -o /dev/null 2>&1 | \
+; RUN:   FileCheck %s --check-prefix=O0-WITHOUT-ENABLE-CFI-INSTR-INSERTER
+
+; RUN: llc -mtriple=riscv64 -O0  \
+; RUN: --riscv-enable-cfi-instr-inserter=true \
+; RUN: -debug-pass=Structure < %s -o /dev/null 2>&1 | \
+; RUN:   FileCheck %s --check-prefix=O0-ENABLE-CFI-INSTR-INSERTER
+
+; REQUIRES: asserts
+
+; O3-WITHOUT-ENABLE-CFI-INSTR-INSERTER-LABEL: Pass Arguments:
+; NO-O3-WITHOUT-ENABLE-CFI-INSTR-INSERTER: Check CFA info and insert CFI instructions if needed
+; O3-WITHOUT-ENABLE-CFI-INSTR-INSERTER: Insert CFI remember/restore state instructions
+
+; O3-ENABLE-CFI-INSTR-INSERTER-LABEL: Pass Arguments:
+; O3-ENABLE-CFI-INSTR-INSERTER: Check CFA info and insert CFI instructions if needed
+; NO-O3-ENABLE-CFI-INSTR-INSERTER: Insert CFI remember/restore state instructions
+
+; O0-WITHOUT-ENABLE-CFI-INSTR-INSERTER-LABEL: Pass Arguments:
+; NO-O0-WITHOUT-ENABLE-CFI-INSTR-INSERTER: Check CFA info and insert CFI instructions if needed
+; O0-WITHOUT-ENABLE-CFI-INSTR-INSERTER: Insert CFI remember/restore state instructions
+
+; O0-ENABLE-CFI-INSTR-INSERTER-LABEL: Pass Arguments:
+; O0-ENABLE-CFI-INSTR-INSERTER: Check CFA info and insert CFI instructions if needed
+; NO-O0-ENABLE-CFI-INSTR-INSERTER: Insert CFI remember/restore state instructions