[llvm] [AMDGPU] Support true16 spill restore with sram-ecc (PR #165320)

[Jay Foad via llvm-commits]

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@@ -1823,6 +1823,16 @@ void SIRegisterInfo::buildSpillLoadStore(
       }
     }
 
+    Register FinalValueReg = ValueReg;
+    if (LoadStoreOp == AMDGPU::SCRATCH_LOAD_USHORT_SADDR) {
+      // If we are loading 16-bit value with SRAMECC endabled we need a temp
+      // 32-bit VGPR to load and extract 16-bits into the final register.
+      ValueReg = RS->scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, MI,
+                                               false, 0, false);
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jayfoad wrote:

Don't you need AllowSpill=true here, since this might need to use the emergency spill slot to get a VGPR?
```suggestion
      ValueReg = RS->scavengeRegisterBackwards(AMDGPU::VGPR_32RegClass, MI,
                                               false, 0);
```

https://github.com/llvm/llvm-project/pull/165320