[llvm] [MIPS][float] Fixed SingleFloat codegen on N32/N64 targets (PR #140575)

[Davide Mor via llvm-commits]

Tazdevil971 wrote:

I rechecked online and it doesn't appear to be the case. First let me preface this by saying that the N32 has been mostly been lost to time, and I could find very few things on the internet.

That said, online I found this: [MIPSproTM N32 ABI handbook](https://irix7.com/techpubs/007-2816-004.pdf), which is what I used to figure out what parts of the ABI where missing.

>From that book, at page 14, it highlights some differences between the 3 ABIs (O32/N32 and N64, called the 64-bit interface). There you can see that callee saved registers behave weirdly in N32, only even registers from f20 to f31 are callee saved.

Also you can see the same thing at page 10, where it highlights caller/callee saved registers.

Finally it also says the same thing at page 9:
> There are eight callee-saved floating point registers, $f24..$f31 for the 64-bit interface. There are six for the n32 ABI, the six even registers in $f20..$f30.
> [The o32-bit ABI specifies the six even registers, or even/odd pairs, $f20..$f31.]

And if we look at what gcc does, it also uses the same "call used regs" for N32 and O32 FP64, and you can see it [here](https://github.com/gcc-mirror/gcc/blob/e1b9ccaa10df0192d8c4818258510821727a3de2/gcc/config/mips/mips.cc#L21123) (I hope this is the right place, I'm not very familiar with the gcc codebase).

So no, in my opinion, N32 and N64 do not use the same FP ABI. Instead the N32 FP ABI is a lot more like the O32 F64 ABI.

https://github.com/llvm/llvm-project/pull/140575