[llvm] [MIPS][float] Fixed SingleFloat codegen on N32/N64 targets (PR #140575)

[Davide Mor via llvm-commits]

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@@ -357,13 +359,19 @@ def CSR_O32_FP64 :
   CalleeSavedRegs<(add (decimate (sequence "D%u_64", 30, 20), 2), RA, FP,
                        (sequence "S%u", 7, 0))>;
 
-def CSR_N32 : CalleeSavedRegs<(add D20_64, D22_64, D24_64, D26_64, D28_64,
-                                   D30_64, RA_64, FP_64, GP_64,
-                                   (sequence "S%u_64", 7, 0))>;
+def CSR_N32 : CalleeSavedRegs<(add(decimate(sequence "D%u_64", 30, 20), 2),
+                  RA_64, FP_64, GP_64, (sequence "S%u_64", 7, 0))>;
+
+def CSR_N32_SingleFloat
+    : CalleeSavedRegs<(add(decimate(sequence "F%u", 30, 20), 2), RA_64, FP_64,
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Tazdevil971 wrote:

I wrote a summary of why I don't think this is the case [here](https://github.com/llvm/llvm-project/pull/140575#issuecomment-3342058261).

https://github.com/llvm/llvm-project/pull/140575