[llvm] [MIPS][float] Fixed SingleFloat codegen on N32/N64 targets (PR #140575)

[YunQiang Su via llvm-commits]

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@@ -342,8 +344,8 @@ def CC_Mips : CallingConv<[
 // Callee-saved register lists.
 //===----------------------------------------------------------------------===//
 
-def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
-                                               (sequence "S%u", 7, 0))>;
+def CSR_O32_SingleFloat : CalleeSavedRegs<(add(sequence "F%u", 31, 20), RA, FP,
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wzssyqa wrote:

I guess it should be for N32?

https://github.com/llvm/llvm-project/pull/140575