[clang] [llvm] [mlir] [AMDGPU] [ROCDL] Added Intrinsics for smed, umed, to support ISA instructions from ROCDL (PR #157748)

[Keshav Vinayak Jha via llvm-commits]

keshavvinayak01 wrote:

> It is not necessary to add new intrinsics for these operations. You are better off writing the med3 in terms of min and max and letting the backend deal with it. The effort of fully supporting all analyses and optimizations on a new operation is very high

So you're suggesting I rewrite the rocdl -> llvmir to use min/max ops in LLVMIR? 
I do think it's still useful to introduce the rocdl ops, see [#157052](https://github.com/llvm/llvm-project/issues/157052)

https://github.com/llvm/llvm-project/pull/157748