[clang] [llvm] [mlir] [AMDGPU] [ROCDL] Added Intrinsics for smed, umed, to support ISA instructions from ROCDL (PR #157748)

[Krzysztof Drewniak via llvm-commits]

krzysz00 wrote:

If the backend can reliably produce med3 out of min and max, then we shouldn't be adding intrinsics - let the compiler do its thing

https://github.com/llvm/llvm-project/pull/157748