[clang] [llvm] [mlir] [AMDGPU] [ROCDL] Added Intrinsics for smed, umed, to support ISA instructions from ROCDL (PR #157748)

[Matt Arsenault via llvm-commits]

arsenm wrote:

>  Why can't we also add similar intrinsics for SMED and UMED when the hardware already supports those instructions?

We probably shouldn't have or use the fmed3 intrinsic. The fmed3 case is special due to the unreasonable signaling nan behavior. The full work to optimize around that was also never implemented 

https://github.com/llvm/llvm-project/pull/157748