[llvm] [AArch64] Combine signext_inreg of setcc(... != splat(0)) (PR #157665)

[Hari Limaye via llvm-commits]

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@@ -41,7 +40,6 @@ define void @test_masked_store_success_v4i32(<4 x i32> %x, ptr %ptr, <4 x i1> %m
 ; SVE-NEXT:    ptrue p0.s, vl4
 ; SVE-NEXT:    // kill: def $q0 killed $q0 def $z0
 ; SVE-NEXT:    shl v1.4s, v1.4s, #31
-; SVE-NEXT:    cmlt v1.4s, v1.4s, #0
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hazzlim wrote:

Regarding killing off the SHL - I was originally thinking that we could do this, i.e. eliminate the SIGN_EXTEND_INREG entirely. However, I'm not sure that it's the case that we can assume that the high bits of the promoted i1->i8 parameter will be set such that this is safe to do - is this well defined by some ABI?

This comment seems to suggest that we cannot assume the top bits to be zeroed: https://github.com/llvm/llvm-project/blob/d6d0f4f156e27e5171475d229b8ea2616c2b3d0c/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp#L3416-L3420

But maybe its safe to assume that the mask is always going to be come from a fcmp/icmp in LLVM IR, which will be lowered to a vector CMP/FCMP instruction. And as the result of these is always 0 or -1, we can guarantee it's essentially already sign extended?

https://github.com/llvm/llvm-project/pull/157665