[llvm] [AArch64] Combine signext_inreg of setcc(... != splat(0)) (PR #157665)

[David Sherwood via llvm-commits]

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@@ -26097,6 +26097,17 @@ static SDValue performSetCCPunpkCombine(SDNode *N, SelectionDAG &DAG) {
   return SDValue();
 }
 
+static bool isSignExtInReg(const SDValue &V) {
+  if (V.getOpcode() != AArch64ISD::VASHR ||
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david-arm wrote:

OK I see, I'll have a think about it some more then. It just feels like the sort of thing we ought to be fixing earlier on using generic ISD nodes. In reality the predicate could come from two different sources:

1. If this is a tail-folded loop then the predicate will be a PHI and so it will be a similar lowering problem to passing as a register argument to a function.
2. In the loop we have a fcmp or icmp, which is used as the input for the masked load.

Ideally we'd be able to handle both.

https://github.com/llvm/llvm-project/pull/157665