[llvm] [RISCV] Use C.ADD when OR is not compressible due to register restriction (PR #156044)

[Sam Elliott via llvm-commits]

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@@ -1178,7 +1178,21 @@ bool RISCVAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
   if (lowerRISCVVMachineInstrToMCInst(MI, OutMI, STI))
     return false;
 
-  OutMI.setOpcode(MI->getOpcode());
+  unsigned Opcode = MI->getOpcode();
+  // If we have a disjoint OR which isn't compressible as an c.or, we can
+  // convert it to a c.add which doesn't have the gprc register restriction.
+  if (STI->hasStdExtZca() && Opcode == RISCV::OR &&
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lenary wrote:

> Not changing register allocation for now. I'm expecting to return to the register allocation in an upcoming patch; I was just staging work to make the diff more understandable. Does this change your take at all?

Not fundamentally - any changes to the register allocation would be in a completely different part of the codebase anyway, and would still need code in a later pass to turn or+disjoint into add.

> [RISCVMakeCompressible] only performs size optimizations, and the while this change does improve size, it's not gated on any of the Os/Oz flags.

Sure, but this patch is still an optimisation about trying to make a specific pattern more amenable to future compression - your code is introducing `add` with the knowledge that the compress patterns for `add` cover more instances of the instruction vs the compress patterns for `or`, which to my mind is essentially what `RISCVMakeCompressible` is doing.

I don't entirely understand why this optimisation warrants a more special treatment than those in RISCVMakeCompressible.


https://github.com/llvm/llvm-project/pull/156044