[llvm] [RISCV] Use C.ADD when OR is not compressible due to register restriction (PR #156044)

[Philip Reames via llvm-commits]

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@@ -1178,7 +1178,21 @@ bool RISCVAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
   if (lowerRISCVVMachineInstrToMCInst(MI, OutMI, STI))
     return false;
 
-  OutMI.setOpcode(MI->getOpcode());
+  unsigned Opcode = MI->getOpcode();
+  // If we have a disjoint OR which isn't compressible as an c.or, we can
+  // convert it to a c.add which doesn't have the gprc register restriction.
+  if (STI->hasStdExtZca() && Opcode == RISCV::OR &&
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preames wrote:

When looking at this code, noticed a cleanup of the existing code: https://github.com/llvm/llvm-project/pull/156482

Honestly, I don't really get your objection to this change at all so I suspect we're talking past each other.  You'd previously said this routine was "mostly a rote function, and I don't think users would expect changes to happen in it".  This routine already lowers all the V pseudo's and had special casing for the patchable function entry stuff (admittedly, that I'm now removing in the patch linked above).  The sole caller has custom lowering for a bunch of MIs; this logic could be easily moved there.  Is your objection that I'm adding an optimization into something otherwise purely functional?

> I don't entirely understand why this optimisation warrants a more special treatment than those in RISCVMakeCompressible.

RISCVMakeCompressible is currently gated by MinSize.  That's my entire objection.  If you'd rather that pass had a section which ran unconditionally, and a second which ran only if MinSize, I'm happy to do that.  

https://github.com/llvm/llvm-project/pull/156044