[llvm] [RISCV] Use C.ADD when OR is not compressible due to register restriction (PR #156044)

Philip Reames via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 2 07:44:21 PDT 2025

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https://github.com/preames edited https://github.com/llvm/llvm-project/pull/156044

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