[llvm] [Intrinsics][AArch64] Add intrinsics for masking off aliasing vector lanes (PR #117007)

[Sander de Smalen via llvm-commits]

================
@@ -24188,13 +24186,19 @@ Overview:
 
 Given a vector store to %ptrA followed by a vector load from %ptrB, this
 instruction generates a mask where an active lane indicates that the
-read-after-write sequence can be performed safely for that lane, without the
-danger of it turning into a write-after-read sequence.
+read-after-write sequence can be performed safely for that lane, without a
+read-after-write hazard occurring or a a new store-to-load forwarding hazard
+being introduced.
----------------
sdesmalen-arm wrote:

```suggestion
read-after-write sequence can be performed safely for that lane, without a
read-after-write hazard or a store-to-load forwarding hazard being introduced.
```

https://github.com/llvm/llvm-project/pull/117007