[llvm] [Intrinsics][AArch64] Add intrinsics for masking off aliasing vector lanes (PR #117007)

[Sander de Smalen via llvm-commits]

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@@ -765,3 +765,193 @@ entry:
   %0 = call <vscale x 16 x i1> @llvm.loop.dependence.war.mask.nxv16i1(ptr %a, ptr %b, i64 3)
   ret <vscale x 16 x i1> %0
 }
+
+define <vscale x 1 x i1> @whilewr_8_scalarize(ptr %a, ptr %b) {
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sdesmalen-arm wrote:

This is not scalarizing a `<vscale x 1 x i1>` type, instead it seems to default to `expand`. I'm not sure how useful these tests are tbh, because this functionality should already be tested elsewhere, so maybe just remove them.

https://github.com/llvm/llvm-project/pull/117007