[llvm] [ARM] Add missing optimize compare candidates to isOptimizeCompareCandidates (PR #155886)
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Sat Aug 30 08:04:42 PDT 2025
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/155886
>From 421565f0908fbe1e14fc6ddcc7715a7391ec80f7 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 28 Aug 2025 12:50:30 -0400
Subject: [PATCH 1/7] Pre-commit tests (NFC)
---
llvm/test/CodeGen/ARM/peephole-rsb.ll | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
create mode 100644 llvm/test/CodeGen/ARM/peephole-rsb.ll
diff --git a/llvm/test/CodeGen/ARM/peephole-rsb.ll b/llvm/test/CodeGen/ARM/peephole-rsb.ll
new file mode 100644
index 0000000000000..7e5ba56a2f7ca
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/peephole-rsb.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+v4t -verify-machineinstrs | FileCheck %s
+
+define i8 @abd_ext_i8_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_ext_i8_i8:
+; CHECK: @ %bb.0:
+; CHECK-NEXT: lsl r0, r0, #24
+; CHECK-NEXT: lsl r1, r1, #24
+; CHECK-NEXT: asr r0, r0, #24
+; CHECK-NEXT: sub r0, r0, r1, asr #24
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: rsbmi r0, r0, #0
+; CHECK-NEXT: bx lr
+ %aext = sext i8 %a to i64
+ %bext = sext i8 %b to i64
+ %sub = sub i64 %aext, %bext
+ %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+ %trunc = trunc i64 %abs to i8
+ ret i8 %trunc
+}
>From 0c8a3e6115bc2b7a75604a28d5b1fb33c5180b55 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 28 Aug 2025 12:52:09 -0400
Subject: [PATCH 2/7] [ARM] Add missing optimize compare candidates to
isOptimizeCompareCandidate
I noticed some were missing when one of the IR I was working on did not optimize it.
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 8 ++++++++
llvm/test/CodeGen/ARM/peephole-rsb.ll | 3 +--
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 9e4dbecc16a87..62ec29142d6a6 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2790,23 +2790,31 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
[[fallthrough]];
case ARM::RSBrr:
case ARM::RSBri:
+ case ARM::RSBrsi:
+ case ARM::RSBrsr:
case ARM::RSCrr:
case ARM::RSCri:
case ARM::ADDrr:
case ARM::ADDri:
+ case ARM::ADDrsi:
+ case ARM::ADDrsr:
case ARM::ADCrr:
case ARM::ADCri:
case ARM::SUBrr:
case ARM::SUBri:
+ case ARM::SUBrsr:
+ case ARM::SUBrsi:
case ARM::SBCrr:
case ARM::SBCri:
case ARM::t2RSBri:
case ARM::t2ADDrr:
case ARM::t2ADDri:
+ case ARM::t2ADDSrs:
case ARM::t2ADCrr:
case ARM::t2ADCri:
case ARM::t2SUBrr:
case ARM::t2SUBri:
+ case ARM::t2SUBSrs:
case ARM::t2SBCrr:
case ARM::t2SBCri:
case ARM::ANDrr:
diff --git a/llvm/test/CodeGen/ARM/peephole-rsb.ll b/llvm/test/CodeGen/ARM/peephole-rsb.ll
index 7e5ba56a2f7ca..91ba40e16761a 100644
--- a/llvm/test/CodeGen/ARM/peephole-rsb.ll
+++ b/llvm/test/CodeGen/ARM/peephole-rsb.ll
@@ -7,8 +7,7 @@ define i8 @abd_ext_i8_i8(i8 %a, i8 %b) nounwind {
; CHECK-NEXT: lsl r0, r0, #24
; CHECK-NEXT: lsl r1, r1, #24
; CHECK-NEXT: asr r0, r0, #24
-; CHECK-NEXT: sub r0, r0, r1, asr #24
-; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: subs r0, r0, r1, asr #24
; CHECK-NEXT: rsbmi r0, r0, #0
; CHECK-NEXT: bx lr
%aext = sext i8 %a to i64
>From 0fb9470a4480c27c7f2d512dbda399190368dfed Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 28 Aug 2025 19:00:41 -0400
Subject: [PATCH 3/7] Update ARMBaseInstrInfo.cpp
Co-authored-by: Eli Friedman <efriedma at quicinc.com>
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 62ec29142d6a6..61179804c7884 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2814,7 +2814,7 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
case ARM::t2ADCri:
case ARM::t2SUBrr:
case ARM::t2SUBri:
- case ARM::t2SUBSrs:
+ case ARM::t2SUBrs:
case ARM::t2SBCrr:
case ARM::t2SBCri:
case ARM::ANDrr:
>From 0a23049c43a08fe5370c87d158cd81ac23bb9a8b Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 28 Aug 2025 19:00:48 -0400
Subject: [PATCH 4/7] Update ARMBaseInstrInfo.cpp
Co-authored-by: Eli Friedman <efriedma at quicinc.com>
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 61179804c7884..0938ab2c0348e 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2809,7 +2809,7 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
case ARM::t2RSBri:
case ARM::t2ADDrr:
case ARM::t2ADDri:
- case ARM::t2ADDSrs:
+ case ARM::t2ADDrs:
case ARM::t2ADCrr:
case ARM::t2ADCri:
case ARM::t2SUBrr:
>From a42de5b320a9d03b7454a1ce43d25ab1d19df006 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Fri, 29 Aug 2025 11:21:22 -0400
Subject: [PATCH 5/7] Update ARMBaseInstrInfo.cpp
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 0938ab2c0348e..47a16ebeeec71 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2851,6 +2851,13 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
case ARM::t2LSLrr:
case ARM::MOVsr:
case ARM::MOVsi:
+ case ARM::SBCrsi:
+ case ARM::SBCrsr:
+ case ARM::RSCrsr:
+ case ARM::RSCrsi:
+ case ARM::t2RSBrr:
+ case ARM::t2RSBrs:
+ case ARM::t2SBCrs:
return true;
}
}
>From 71a6bb9fbdb8a6b44cc418cb07550ef61fdfce29 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 30 Aug 2025 11:00:28 -0400
Subject: [PATCH 6/7] Update ARMBaseInstrInfo.cpp
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 47a16ebeeec71..0c4cfaa0c50c2 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2274,6 +2274,7 @@ static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
{ARM::SUBSrsr, ARM::SUBrsr},
{ARM::RSBSri, ARM::RSBri},
+ {ARM::RSBSrr, ARM::RSBrr},
{ARM::RSBSrsi, ARM::RSBrsi},
{ARM::RSBSrsr, ARM::RSBrsr},
@@ -2298,6 +2299,7 @@ static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
{ARM::t2SUBSrs, ARM::t2SUBrs},
{ARM::t2RSBSri, ARM::t2RSBri},
+ {ARM::t2RSBSrr, ARM::t2RSBrr},
{ARM::t2RSBSrs, ARM::t2RSBrs},
};
@@ -2794,6 +2796,8 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
case ARM::RSBrsr:
case ARM::RSCrr:
case ARM::RSCri:
+ case ARM::RSCrsr:
+ case ARM::RSCrsi:
case ARM::ADDrr:
case ARM::ADDri:
case ARM::ADDrsi:
@@ -2806,7 +2810,11 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
case ARM::SUBrsi:
case ARM::SBCrr:
case ARM::SBCri:
+ case ARM::SBCrsi:
+ case ARM::SBCrsr:
case ARM::t2RSBri:
+ case ARM::t2RSBrr:
+ case ARM::t2RSBrs:
case ARM::t2ADDrr:
case ARM::t2ADDri:
case ARM::t2ADDrs:
@@ -2817,6 +2825,7 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
case ARM::t2SUBrs:
case ARM::t2SBCrr:
case ARM::t2SBCri:
+ case ARM::t2SBCrs:
case ARM::ANDrr:
case ARM::ANDri:
case ARM::ANDrsr:
@@ -2851,13 +2860,6 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
case ARM::t2LSLrr:
case ARM::MOVsr:
case ARM::MOVsi:
- case ARM::SBCrsi:
- case ARM::SBCrsr:
- case ARM::RSCrsr:
- case ARM::RSCrsi:
- case ARM::t2RSBrr:
- case ARM::t2RSBrs:
- case ARM::t2SBCrs:
return true;
}
}
>From 902e52709e818a60d798ac9136d2231a8acfcef2 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 30 Aug 2025 11:04:29 -0400
Subject: [PATCH 7/7] Update ARMBaseInstrInfo.cpp
---
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 --
1 file changed, 2 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 0c4cfaa0c50c2..aa4478fee432a 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2274,7 +2274,6 @@ static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
{ARM::SUBSrsr, ARM::SUBrsr},
{ARM::RSBSri, ARM::RSBri},
- {ARM::RSBSrr, ARM::RSBrr},
{ARM::RSBSrsi, ARM::RSBrsi},
{ARM::RSBSrsr, ARM::RSBrsr},
@@ -2299,7 +2298,6 @@ static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
{ARM::t2SUBSrs, ARM::t2SUBrs},
{ARM::t2RSBSri, ARM::t2RSBri},
- {ARM::t2RSBSrr, ARM::t2RSBrr},
{ARM::t2RSBSrs, ARM::t2RSBrs},
};
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