[llvm] [ARM] Add missing optimize compare candidates to isOptimizeCompareCandidates (PR #155886)

[via llvm-commits]

https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/155886

>From 421565f0908fbe1e14fc6ddcc7715a7391ec80f7 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 28 Aug 2025 12:50:30 -0400
Subject: [PATCH 1/2] Pre-commit tests (NFC)

---
 llvm/test/CodeGen/ARM/peephole-rsb.ll | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)
 create mode 100644 llvm/test/CodeGen/ARM/peephole-rsb.ll

diff --git a/llvm/test/CodeGen/ARM/peephole-rsb.ll b/llvm/test/CodeGen/ARM/peephole-rsb.ll
new file mode 100644
index 0000000000000..7e5ba56a2f7ca
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/peephole-rsb.ll
@@ -0,0 +1,20 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=arm-eabi -mattr=+v4t -verify-machineinstrs | FileCheck %s
+
+define i8 @abd_ext_i8_i8(i8 %a, i8 %b) nounwind {
+; CHECK-LABEL: abd_ext_i8_i8:
+; CHECK:       @ %bb.0:
+; CHECK-NEXT:    lsl r0, r0, #24
+; CHECK-NEXT:    lsl r1, r1, #24
+; CHECK-NEXT:    asr r0, r0, #24
+; CHECK-NEXT:    sub r0, r0, r1, asr #24
+; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    rsbmi r0, r0, #0
+; CHECK-NEXT:    bx lr
+  %aext = sext i8 %a to i64
+  %bext = sext i8 %b to i64
+  %sub = sub i64 %aext, %bext
+  %abs = call i64 @llvm.abs.i64(i64 %sub, i1 false)
+  %trunc = trunc i64 %abs to i8
+  ret i8 %trunc
+}

>From 44fe6defc83c3a6494d32f8b08946ca4c09b5b1a Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Thu, 28 Aug 2025 12:52:09 -0400
Subject: [PATCH 2/2] [ARM] Add missing optimize compare candidates to
 isOptimizeCompareCandidate

I noticed some were missing when one of the IR I was working on did not optimize it.

Co-Authored-By: Eli Friedman <efriedma at quicinc.com>
---
 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 15 +++++++++++++++
 llvm/test/CodeGen/ARM/peephole-rsb.ll    |  3 +--
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 9e4dbecc16a87..aa4478fee432a 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -2790,25 +2790,40 @@ static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
     [[fallthrough]];
   case ARM::RSBrr:
   case ARM::RSBri:
+  case ARM::RSBrsi:
+  case ARM::RSBrsr:
   case ARM::RSCrr:
   case ARM::RSCri:
+  case ARM::RSCrsr:
+  case ARM::RSCrsi:
   case ARM::ADDrr:
   case ARM::ADDri:
+  case ARM::ADDrsi:
+  case ARM::ADDrsr:
   case ARM::ADCrr:
   case ARM::ADCri:
   case ARM::SUBrr:
   case ARM::SUBri:
+  case ARM::SUBrsr:
+  case ARM::SUBrsi:
   case ARM::SBCrr:
   case ARM::SBCri:
+  case ARM::SBCrsi:
+  case ARM::SBCrsr:
   case ARM::t2RSBri:
+  case ARM::t2RSBrr:
+  case ARM::t2RSBrs:
   case ARM::t2ADDrr:
   case ARM::t2ADDri:
+  case ARM::t2ADDrs:
   case ARM::t2ADCrr:
   case ARM::t2ADCri:
   case ARM::t2SUBrr:
   case ARM::t2SUBri:
+  case ARM::t2SUBrs:
   case ARM::t2SBCrr:
   case ARM::t2SBCri:
+  case ARM::t2SBCrs:
   case ARM::ANDrr:
   case ARM::ANDri:
   case ARM::ANDrsr:
diff --git a/llvm/test/CodeGen/ARM/peephole-rsb.ll b/llvm/test/CodeGen/ARM/peephole-rsb.ll
index 7e5ba56a2f7ca..91ba40e16761a 100644
--- a/llvm/test/CodeGen/ARM/peephole-rsb.ll
+++ b/llvm/test/CodeGen/ARM/peephole-rsb.ll
@@ -7,8 +7,7 @@ define i8 @abd_ext_i8_i8(i8 %a, i8 %b) nounwind {
 ; CHECK-NEXT:    lsl r0, r0, #24
 ; CHECK-NEXT:    lsl r1, r1, #24
 ; CHECK-NEXT:    asr r0, r0, #24
-; CHECK-NEXT:    sub r0, r0, r1, asr #24
-; CHECK-NEXT:    cmp r0, #0
+; CHECK-NEXT:    subs r0, r0, r1, asr #24
 ; CHECK-NEXT:    rsbmi r0, r0, #0
 ; CHECK-NEXT:    bx lr
   %aext = sext i8 %a to i64