[llvm] [AArch64][SDAG] Add f16 -> i16 rounding NEON conversion intrinsics (PR #155851)

[David Green via llvm-commits]

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@@ -28292,6 +28306,30 @@ void AArch64TargetLowering::ReplaceNodeResults(
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));
       return;
     }
+    case Intrinsic::aarch64_neon_fcvtzs: {
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davemgreen wrote:

If it is done as a combine it might help constant fold or optimize the instruction. It's unlikely, but it might come up from time to time. If it was done in lowering then yeah, there is less point in going via fptosi.sat.

If they are equivalent then we could think of just emitting the saturating convert in clang and avoid the neon intrinsics entirely.

https://github.com/llvm/llvm-project/pull/155851