[llvm] [AArch64][SDAG] Add f16 -> i16 rounding NEON conversion intrinsics (PR #155851)

[Kajetan Puchalski via llvm-commits]

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@@ -28292,6 +28306,30 @@ void AArch64TargetLowering::ReplaceNodeResults(
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));
       return;
     }
+    case Intrinsic::aarch64_neon_fcvtzs: {
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mrkajetanp wrote:

My rationale for this was that fptosi.sat will be replaced with these same nodes regardless so replacing the intrinsic with the nodes directly skips a step and saves some cycles. Would we rather go through fptosi.sat?

https://github.com/llvm/llvm-project/pull/155851