[llvm] [AArch64][SDAG] Add f16 -> i16 rounding NEON conversion intrinsics (PR #155851)

[Kajetan Puchalski via llvm-commits]

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@@ -28292,6 +28306,30 @@ void AArch64TargetLowering::ReplaceNodeResults(
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, VT, V));
       return;
     }
+    case Intrinsic::aarch64_neon_fcvtzs: {
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mrkajetanp wrote:

My thinking was to emit the node directly for aarch64_neon_fcvtzs in the backend, but then in clang consider whether to just generate fptosi.sat. I'm not particularly strongly opinionated on this though, so I'm happy to adjust this whichever way you'd prefer.

https://github.com/llvm/llvm-project/pull/155851