[llvm] [AArch64][SDAG] Lower f16->s16 FP_TO_INT_SAT to *v1f16 (PR #154822)

[David Green via llvm-commits]

================
@@ -6539,6 +6542,18 @@ defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
 def : Pat<(v1i64 (AArch64vashr (v1i64 V64:$Rn), (i32 63))),
           (CMLTv1i64rz V64:$Rn)>;
 
+// f16 -> s16 conversions leave the bit pattern in a f32
+class F16ToS16ScalarPat<SDNode cvt_isd, BaseSIMDTwoScalar instr>
+    : Pat<(f32 (cvt_isd (f16 FPR16:$Rn))),
+    (EXTRACT_SUBREG
+     (v8f16 (SUBREG_TO_REG (i64 0), (instr FPR16:$Rn), hsub)),
+     ssub)>;
----------------
davemgreen wrote:

I think `(f32 (SUBREG_TO_REG (i64 0), (instr FPR16:$Rn), hsub))` might be enough?
(I also like it when Pats have obvious and aligned input and output lines, but that is very minor). Something like
```
  : Pat<(f32 (cvt_isd (f16 FPR16:$Rn))),
        (f32 (SUBREG_TO_REG (i64 0), (instr FPR16:$Rn), hsub))>;
```

https://github.com/llvm/llvm-project/pull/154822