[llvm] [AArch64][SDAG] Lower f16->s16 FP_TO_INT_SAT to *v1f16 (PR #154822)

[David Green via llvm-commits]

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@@ -4911,6 +4911,15 @@ SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
   if (DstWidth < SatWidth)
     return SDValue();
 
+  if (SrcVT == MVT::f16 && SatVT == MVT::i16 && DstVT == MVT::i32) {
+    SDValue CVTf32;
+    if (Op.getOpcode() == ISD::FP_TO_SINT_SAT)
+      CVTf32 = DAG.getNode(AArch64ISD::FCVTZS_HALF, DL, MVT::f32, SrcVal);
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davemgreen wrote:

Does the signed version need to sign_ext the result (or some form of sign_ext_inreg)?
AFAUI the new node will set the upper bits of the resulting f32/i32 register to 0 as it only writes f16, which is fine for U but not for S. The sign extend might be lost along the way into the `i32 = fp_to_sint_sat t2, ValueType:ch:i16`

https://github.com/llvm/llvm-project/pull/154822