[llvm] [AArch64][SDAG] Lower f16->s16 FP_TO_INT_SAT to *v1f16 (PR #154822)

[David Green via llvm-commits]

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@@ -4911,6 +4911,15 @@ SDValue AArch64TargetLowering::LowerFP_TO_INT_SAT(SDValue Op,
   if (DstWidth < SatWidth)
     return SDValue();
 
+  if (SrcVT == MVT::f16 && SatVT == MVT::i16 && DstVT == MVT::i32) {
+    SDValue CVTf32;
+    if (Op.getOpcode() == ISD::FP_TO_SINT_SAT)
+      CVTf32 = DAG.getNode(AArch64ISD::FCVTZS_HALF, DL, MVT::f32, SrcVal);
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davemgreen wrote:

I would keep it as a f32 I think. (It would be nice to be able to produce a f16, but we can't bitcast that to an i16). It is generally better to have simpler patterns that produce a single instruction - it means we might be able to remove/optimize the sext in some situations.

https://github.com/llvm/llvm-project/pull/154822