[llvm] [RISCV] Add SRAW to ComputeNumSignBitsForTargetNode. (PR #155564)

[Philip Reames via llvm-commits]

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@@ -220,3 +220,18 @@ define signext i32 @test14(ptr %0, ptr %1, i64 %2) {
   %12 = add i32 %9, %11
   ret i32 %12
 }
+
+; Test that we can propagate sign bits through sraw. We should use an slli
+; instead of slliw.
+define signext i32 @test15(i32 signext %x, i32 signext %y) {
+; RV64I-LABEL: test15:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srli a0, a0, 1
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preames wrote:

Not directly related, but how did we figure out this could be a srli?  The test is written as an ashr, and yet we turned it into a logical shift?  And if we recognized it was a logical shift, why can't we recognize the next one is too?  (Since the sign bit is now known.)  

https://github.com/llvm/llvm-project/pull/155564