[llvm] [RISCV] Add SRAW to ComputeNumSignBitsForTargetNode. (PR #155564)

[Craig Topper via llvm-commits]

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@@ -220,3 +220,18 @@ define signext i32 @test14(ptr %0, ptr %1, i64 %2) {
   %12 = add i32 %9, %11
   ret i32 %12
 }
+
+; Test that we can propagate sign bits through sraw. We should use an slli
+; instead of slliw.
+define signext i32 @test15(i32 signext %x, i32 signext %y) {
+; RV64I-LABEL: test15:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    srli a0, a0, 1
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topperc wrote:

Because the input is marked sign extend with `signext`, we know that the promoted shift by 1 has bit 63:31 all the same in its input. So shifting by 1 will move bit 32 into bit 31 which we just said is the same so we don't need to use sraiw and can use srai.

The sraw only uses bits 31:0 of the srai result so it doesn't matter what gets shifted into bit 63. So the srai can be a srli.

I'm not sure we can do anything to the sraw. We only know bit 63 of its input is zero, but it doesn't use bit 63.

While thinking through this, I think the optimization I added here must be happening before the srai becomes srli. Once it becomes srli we only know the input to the sraw has 1 sign bit, not 34 sign bits.

https://github.com/llvm/llvm-project/pull/155564