[llvm] [RISCV] Add riscv_masked_atomicrmw_*_i64 to getTgtMemIntrinsic. (PR #154805)

[Craig Topper via llvm-commits]

https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/154805

>From de4a739cc4c91fca4e8624eb49e358f36979e8ae Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Thu, 21 Aug 2025 10:50:24 -0700
Subject: [PATCH] [RISCV] Add riscv_masked_atomicrmw_*_i64 to
 getTgtMemIntrinsic.

---
 llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4a1db80076530..ff625a8bcda30 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1809,6 +1809,15 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
   case Intrinsic::riscv_masked_atomicrmw_umax_i32:
   case Intrinsic::riscv_masked_atomicrmw_umin_i32:
   case Intrinsic::riscv_masked_cmpxchg_i32:
+  case Intrinsic::riscv_masked_atomicrmw_xchg_i64:
+  case Intrinsic::riscv_masked_atomicrmw_add_i64:
+  case Intrinsic::riscv_masked_atomicrmw_sub_i64:
+  case Intrinsic::riscv_masked_atomicrmw_nand_i64:
+  case Intrinsic::riscv_masked_atomicrmw_max_i64:
+  case Intrinsic::riscv_masked_atomicrmw_min_i64:
+  case Intrinsic::riscv_masked_atomicrmw_umax_i64:
+  case Intrinsic::riscv_masked_atomicrmw_umin_i64:
+  case Intrinsic::riscv_masked_cmpxchg_i64:
     Info.opc = ISD::INTRINSIC_W_CHAIN;
     Info.memVT = MVT::i32;
     Info.ptrVal = I.getArgOperand(0);