[llvm] [RISCV] Add riscv_masked_atomicrmw_*_i64 to getTgtMemIntrinsic. (PR #154805)

[Craig Topper via llvm-commits]

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@@ -1809,6 +1809,15 @@ bool RISCVTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
   case Intrinsic::riscv_masked_atomicrmw_umax_i32:
   case Intrinsic::riscv_masked_atomicrmw_umin_i32:
   case Intrinsic::riscv_masked_cmpxchg_i32:
+  case Intrinsic::riscv_masked_atomicrmw_xchg_i64:
+  case Intrinsic::riscv_masked_atomicrmw_add_i64:
+  case Intrinsic::riscv_masked_atomicrmw_sub_i64:
+  case Intrinsic::riscv_masked_atomicrmw_nand_i64:
+  case Intrinsic::riscv_masked_atomicrmw_max_i64:
+  case Intrinsic::riscv_masked_atomicrmw_min_i64:
+  case Intrinsic::riscv_masked_atomicrmw_umax_i64:
+  case Intrinsic::riscv_masked_atomicrmw_umin_i64:
+  case Intrinsic::riscv_masked_cmpxchg_i64:
     Info.opc = ISD::INTRINSIC_W_CHAIN;
     Info.memVT = MVT::i32;
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topperc wrote:

I don't know if you've seen it yet, but I also posted https://github.com/llvm/llvm-project/pull/154845 to merge these using type overloading.

https://github.com/llvm/llvm-project/pull/154805