[llvm] AMDGPU: Add pseudoinstruction for 64-bit agpr or vgpr constants (PR #154499)

[Janek van Oirschot via llvm-commits]

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@@ -160,6 +160,26 @@ def AV_MOV_B32_IMM_PSEUDO
   let UseNamedOperandTable = 1;
 }
 
+// 64-bit materialize immediate which supports AGPR or VGPR. This has
+// an unusual operand restriction which requires the two halves of the
+// immediate to each be 32-bit inline immediate values.
+//
+// FIXME: This unnecessarily has the even aligned vector register
+// requirement applied.
+def AV_MOV_B64_IMM_PSEUDO
+    : VPseudoInstSI<(outs AV_64:$vdst), (ins AV_64_PSEUDO_IMM:$src0)> {
+  let isReMaterializable = 1;
+  let isAsCheapAsAMove = 1;
+
+  // Imprecise, technically if AGPR it's VOP3 and VOP1 for AGPR. But
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JanekvO wrote:

`if AGPR it's VOP3 and VOP1 for AGPR`
I don't understand this. Is this a typo? Should one of them be VGPR?

https://github.com/llvm/llvm-project/pull/154499