[llvm] [RISCV][GlobalISel] Legalize and select G_ATOMICRMW_ADD instruction (PR #153791)

[Craig Topper via llvm-commits]

================
@@ -692,6 +692,11 @@ RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST)
       .customIf(all(typeIsLegalIntOrFPVec(0, IntOrFPVecTys, ST),
                     typeIsLegalIntOrFPVec(1, IntOrFPVecTys, ST)));
 
+  getActionDefinitionsBuilder(G_ATOMICRMW_ADD)
+      .legalFor(ST.hasStdExtA(), {{s32, p0}, {sXLen, p0}})
+      .libcallFor(!ST.hasStdExtA(), {{s8, p0}, {s16, p0}, {s32, p0}, {s64, p0}})
+      .clampScalar(0, s32, sXLen);
----------------
topperc wrote:

This should fix the i32 selection problem on RV64. All of the SelectionDAG patterns are expecting SXLen so we need to widen to sXLen not s32.

```suggestion
  getActionDefinitionsBuilder(G_ATOMICRMW_ADD)
      .legalFor(ST.hasStdExtA(), {{sXLen, p0}})
      .libcallFor(!ST.hasStdExtA(), {{s8, p0}, {s16, p0}, {s32, p0}, {s64, p0}})
      .clampScalar(0, sXLen, sXLen);
```

https://github.com/llvm/llvm-project/pull/153791