[llvm] [AArch64] Support scalable vp.udiv/vp.sdiv with SVE (PR #154327)

[Paul Walker via llvm-commits]

https://github.com/paulwalker-arm requested changes to this pull request.

There needs to be wider discussion before going down this path.  We've currently avoided adding AArch64 code generation support for the VP intrinsics because it is unclear what agreement is in place for them to be "the" solution to supporting masked operations within LLVM IR.

It's not a deal breaker but I've never much like the EVL parameter, or at least the way it is defined.  This is because, as you say, for SVE it is meaningless and I don't like having meaningless properties within the IR.

Looking at the current code I think AArch64 isel is just missing PatFrags for select based divides, much like we have for select based add, subs etc.

https://github.com/llvm/llvm-project/pull/154327