[llvm] [AArch64] Support scalable vp.udiv/vp.sdiv with SVE (PR #154327)

[Luke Lau via llvm-commits]

================
@@ -156,6 +156,17 @@ class AArch64TTIImpl final : public BasicTTIImplBase<AArch64TTIImpl> {
 
   bool isVScaleKnownToBeAPowerOfTwo() const override { return true; }
 
+  TargetTransformInfo::VPLegalization
+  getVPLegalizationStrategy(const VPIntrinsic &PI) const override {
+    using VPLegalization = TargetTransformInfo::VPLegalization;
+    switch (PI.getIntrinsicID()) {
+    case Intrinsic::vp_sdiv:
+    case Intrinsic::vp_udiv:
+      return VPLegalization(VPLegalization::Discard, VPLegalization::Legal);
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lukel97 wrote:

This is just saying that the EVL argument doesn't actually make a difference on SVE because udiv/sdiv doesn't trap anyway, so feel free to throw it away. 

But since sdiv + udiv can have UB on those lanes, ExpandVectorPredication ends up moving the EVL into the mask operand, hence the

```asm
whilelo p1.d, wzr, w0
and p0.b, p1/z, p1.b, p0.b
```

in the tests

https://github.com/llvm/llvm-project/pull/154327